what i read in that post is : The current version boards and parts are in hungary, pilfered by some dude. To solve this problem we're going to make a totally new board, with new and totally different parts ... untested untried and then we will write the HDL. if the hdl doesn't work and we need more resources we will redo the board once again...
The 'run for the hills part' is the following:
Since they don't know what is needed and clearly state they may have to 'respin the hardware, depending on the HDL' this means 1 thing and one thing only : there is NO WORKING HDL (fpga code)!. If there were a completed HDL they would know what is required as far as supporting hardware goes.
So this project is just a blank board and some parts. It has never run , never booted and never captured even one USB packet. it's not even sure the selected fpga and memory is large enough / fast enough or adequate for the task at hand..
pigs flying , thick layers of ice in hell and chickens needing dentists .... something along those lines...
-edit-.. i just looked at the schematics. this thing cannot and will not work... here is why : they take an A side and a B side connector ,string em together and then splice the DP and DM into a 3340 transceiver. YOU CAN NOT DO THAT ! usb is point to point. you can not splice the bus ! you would need two USB transceiver cells. and have the data flow through the FPGA.
Furthermore, the 3340 is only a FULL SPEED transceiver ( USB 1.0 ) . it cannot handle 2.0. for 2.0 it has a built in multiplexer that disconnects itself from the bus and allows an external PHY to take over.
so this thing isn't even 2.0 capable !