Author Topic: openvizsla......... still......  (Read 29641 times)

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Offline swSteve

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Re: openvizsla......... still......
« Reply #25 on: May 30, 2013, 04:36:56 am »
I can see what you're talking about. But this project was sold as open.

An "open" project does not have to be open during the development process, only when complete. (unless they specifically promised otherwise?)
There can in fact be big downsides to going open during the design process, as I can well attest to with my PSU series. You end up with a thousand people screaming at you to do it this way, do it that way, asking questions and demanding things which start getting you off track etc.

Are you the guy that writes those lengthy software licenses with all the asterisks?

OK

We gave those guys more than 2 years which was more than fair and respectful.

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Offline c4757p

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Re: openvizsla......... still......
« Reply #26 on: May 30, 2013, 04:42:56 am »
I can see what you're talking about. But this project was sold as open.

An "open" project does not have to be open during the development process, only when complete. (unless they specifically promised otherwise?)
There can in fact be big downsides to going open during the design process, as I can well attest to with my PSU series. You end up with a thousand people screaming at you to do it this way, do it that way, asking questions and demanding things which start getting you off track etc.

Are you the guy that writes those lengthy software licenses with all the asterisks?

Expecting an "open" project to be open during development unless otherwise specified is like expecting that you can open a gift before you receive it, just because it's going to be yours at some point.
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Offline EEVblog

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Re: openvizsla......... still......
« Reply #27 on: May 30, 2013, 04:55:18 am »
Are you the guy that writes those lengthy software licenses with all the asterisks?

No, I'm the guy that understands the practical reasons for things.

Quote
We gave those guys more than 2 years which was more than fair and respectful.

Sure, you'll get no argument for me.
They should have had the balls to admit long ago that the project was never going to get there, and at that point admit defeat and simply release/ship whatever they had.
 

Offline Smokey

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Re: openvizsla......... still......
« Reply #28 on: August 01, 2013, 07:42:13 pm »
Happened to be looking at another kickstarter and figured I'd check in on OpenVizsla... Check this out...

http://www.kickstarter.com/projects/bushing/openvizsla-open-source-usb-protocol-analyzer/posts/522345

The plot thickens.....
 

Offline Bored@Work

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Re: openvizsla......... still......
« Reply #29 on: August 01, 2013, 08:10:28 pm »
Happened to be looking at another kickstarter and figured I'd check in on OpenVizsla... Check this out...

http://www.kickstarter.com/projects/bushing/openvizsla-open-source-usb-protocol-analyzer/posts/522345

The plot thickens.....

Do you believe the story? Amazing.
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Offline Rasz

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Re: openvizsla......... still......
« Reply #30 on: August 01, 2013, 08:16:21 pm »
cool story, except "Project by bushing", not "project by pytey". This guy is FKCD for the rest of his life now, he is "the guy that defrauder a bunch of people on kickstarter". Nobody cares he send money to some dude in Hungary.

ps: his latest pcb design could be substituted with $40 chinese fpga board + usb phy on separate board = $30000 in hardware. Instead he once again spins some random boards nobody will ever receive.
« Last Edit: August 01, 2013, 08:22:41 pm by Rasz »
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Offline EEVblog

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Re: openvizsla......... still......
« Reply #31 on: August 01, 2013, 09:34:28 pm »
http://www.kickstarter.com/projects/bushing/openvizsla-open-source-usb-protocol-analyzer/posts/522345
The plot thickens.....

Ok, I'll state the bleeding obvious.
If the project can be done with a spartan 6 FPGA and FTDI board and there is enough money left to manufacture them, why not do this:
1) Return the remaining money
2) Continue to do the HDL design based on a standard Spartan 6 FPGA platform (pick one of many) as a show of good faith and release to the wild.
Those who want to then make one can make one, those who don't at least have some money back.

IMO that's the only way to get any shred of credibility back.
 

Offline free_electron

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Re: openvizsla......... still......
« Reply #32 on: August 01, 2013, 09:54:10 pm »
what i read in that post is : The current version boards and parts are in hungary, pilfered by some dude. To solve this problem we're going to make a totally new board, with new and totally different parts ... untested untried and then we will write the HDL. if the hdl doesn't work and we need more resources we will redo the board once again...

The 'run for the hills part' is the following:
Since they don't know what is needed and clearly state they may have to 'respin the hardware, depending on the HDL' this means 1 thing and one thing only : there is NO WORKING HDL (fpga code)!. If there were a completed HDL they would know what is required as far as supporting hardware goes.

So this project is just a blank board and some parts. It has never run , never booted and never captured even one USB packet. it's not even sure the selected fpga and memory is large enough / fast enough or adequate for the task at hand..

pigs flying , thick layers of ice in hell and chickens needing dentists .... something along those lines...

-edit-.. i just looked at the schematics. this thing cannot and will not work... here is why : they take an A side and a B side connector ,string em together and then splice the DP and DM into a 3340 transceiver. YOU CAN NOT DO THAT ! usb is point to point. you can not splice the bus ! you would need two USB transceiver cells. and have the data flow through the FPGA.

Furthermore, the 3340 is only a FULL SPEED transceiver ( USB 1.0 ) . it cannot handle 2.0. for 2.0 it has a built in multiplexer that disconnects itself from the bus and allows an external PHY to take over.

so this thing isn't even 2.0 capable !
« Last Edit: August 01, 2013, 10:11:07 pm by free_electron »
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Offline Bored@Work

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Re: openvizsla......... still......
« Reply #33 on: August 01, 2013, 10:38:48 pm »
what i read in that post is : The current version boards and parts are in hungary,

And the parts are so special, one can't get them in the US of A. Made from some secret Hungarian paprika sauce ... It is the "blame the bloody foreigner" excuse.

Quote
Furthermore, the 3340 is only a FULL SPEED transceiver ( USB 1.0 ) . it cannot handle 2.0. for 2.0 it has a built in multiplexer that disconnects itself from the bus and allows an external PHY to take over.

This is where the secret Hungarian paprika sauce was coming in ...
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Offline Baliszoft

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Re: openvizsla......... still......
« Reply #34 on: August 01, 2013, 10:58:23 pm »
I feel ashamed being a hungarian. and this is not the first time lately
 

alm

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Re: openvizsla......... still......
« Reply #35 on: August 01, 2013, 11:12:23 pm »
-edit-.. i just looked at the schematics. this thing cannot and will not work... here is why : they take an A side and a B side connector ,string em together and then splice the DP and DM into a 3340 transceiver. YOU CAN NOT DO THAT ! usb is point to point. you can not splice the bus ! you would need two USB transceiver cells. and have the data flow through the FPGA.
Agreed. Signal integrity and termination will be terrible, and probably also negotiation.

Furthermore, the 3340 is only a FULL SPEED transceiver ( USB 1.0 ) . it cannot handle 2.0. for 2.0 it has a built in multiplexer that disconnects itself from the bus and allows an external PHY to take over.
The datasheet for the 3343 suggests otherwise. Or did I miss a footnote somewhere?
 

Offline firewalker

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Re: openvizsla......... still......
« Reply #36 on: August 01, 2013, 11:26:57 pm »
I feel ashamed being a hungarian. and this is not the first time lately

Why?

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Offline free_electron

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Re: openvizsla......... still......
« Reply #37 on: August 02, 2013, 12:07:11 am »

Agreed. Signal integrity and termination will be terrible, and probably also negotiation.


That's not it .. There is no menage-a-trois on usb , USB is point to point ! you can not have a third transceiver cell on the pair of wires. even if that transceiver would be listen only. You need to have two transceivers and basically replicate the dataflow. that means all data has to go through the fpga.

you can't simply splice the wires ...

@alm : they are using a 3340 not a 3343 ... look at the block diagram. they clearly show the switch to bring out the DP and DM to wire up to a high speed phy. the internal phy is full speed only.
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Offline krivx

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Re: openvizsla......... still......
« Reply #38 on: August 02, 2013, 12:16:24 am »
@alm : they are using a 3340 not a 3343 ... look at the block diagram. they clearly show the switch to bring out the DP and DM to wire up to a high speed phy. the internal phy is full speed only.

Looks like they switched to a 3343 a month ago, check the list of commits on their github https://github.com/openvizsla/ov_ftdi/tree/master/hardware
 

Online FrankBuss

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Re: openvizsla......... still......
« Reply #39 on: August 02, 2013, 12:20:36 am »
That's not it .. There is no menage-a-trois on usb , USB is point to point ! you can not have a third transceiver cell on the pair of wires. even if that transceiver would be listen only. You need to have two transceivers and basically replicate the dataflow. that means all data has to go through the fpga.
You don't need two transceivers, you could sample the bus. There are differential probes with 1 pF / 1 MOhm: http://www.tek.com/differential-probe I guess would be much less expensive on the board and if you just want to check if it is 1 or 0, and not measuring the eye-diagram etc. But could be tricky for 480 Mbit/s high-speed USB, and the clock regeneration would be hard. Maybe a differential amplifier to decouple it from the USB bus, and then a transceiver chip, if it can work in receive mode, only.
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Offline Short Circuit

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Re: openvizsla......... still......
« Reply #40 on: August 02, 2013, 12:40:34 am »

Agreed. Signal integrity and termination will be terrible, and probably also negotiation.


That's not it .. There is no menage-a-trois on usb , USB is point to point ! you can not have a third transceiver cell on the pair of wires. even if that transceiver would be listen only. You need to have two transceivers and basically replicate the dataflow. that means all data has to go through the fpga.

you can't simply splice the wires ...

Need maybe, but that is not how things are done in commercial USB analyzers.

Here's a couple of pics inside an Ellisys USB1.1 analyzer;
(uses Cypress CY7C68013, Xilinx Spartan XC2S50 and an ISP1107 transceiver)

And a warning from the LeCroy (former CATC) UsbMobile manual:
Quote
USBMobile T2 (and USBMobile HS) USB is not a hub device. It connects to a USB
branch by inserting a non-intrusive, high-impedance tap. Because poor signal quality in
the middle of a USB cable, LeCroy recommends using the shortest possible cables, so
that total length of both cables together is less than six feet. The USB cables provided
with your Analyzer meet this requirement. When longer cables are used, the Analyzer
might record incorrect data.
 

Offline marshallh

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Re: openvizsla......... still......
« Reply #41 on: August 02, 2013, 03:14:46 am »
I have a Usb 3.0 analyzer, it's done via passive tapping as well, though it is quite elaborate and expensive. The signal is redriven right after the passive taps to the DUT. (Reconstructed via active redriver, not just amplified) So the net effect on the signal is nil.
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Offline Bored@Work

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Re: openvizsla......... still......
« Reply #42 on: August 02, 2013, 04:40:05 am »
I feel ashamed being a hungarian. and this is not the first time lately

If that wasn't clear, in my opinion I think it is just a lame excuse to blame it on the Hungarian guy and make him the scapegoat. He might have parts, he might have boards, but it is very unlikely that one can get these alleged very special parts in Hungary only.

The hole reason given by this bushing guy why he needed to do yet another design and board sounds like bullshit to me.
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Offline free_electron

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Re: openvizsla......... still......
« Reply #43 on: August 02, 2013, 06:54:06 am »
I am writing my finding ps based o their latest published schematics. That shows a 3340, not a 3343.

Yes you can passively tap a usb signal. Agilent scopes can sniff usb using two simple passive probes.
Yes you can also use an active amolifier or even a barebones transceiver cell like a philips isp1107.
But you cant do it with that 334x as that thing has logic on board. When it sees a usb packet it will (may) react to it. The isp1107 is a dumb isb compliant differntial driver and differential receiver. You can flick that in receive only mode and bobs your uncle. Note that the isp1107 is full speed only (1.1 : 12 megabit) it cant do high speed 480 megabit 2.0) But, if you want to sniff the high speed usb2.0 (which is 480MHz ) you will need an fpga with a bit more oomph...

This project is a complete fail. They have no clue what hardware they really need, are simply slapping some parts on a board, then will try to write some hdl , very quickly finding out their fpga is too small too slow, the usb phy is incorrect and there is no chance inhell it will do 2.0 .. And then what ' oh we're going to spin the board once more like we said... Burning some more money...

It's dead. Bury it.
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Offline Baliszoft

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Re: openvizsla......... still......
« Reply #44 on: August 02, 2013, 06:56:03 am »
I feel ashamed being a hungarian. and this is not the first time lately

If that wasn't clear, in my opinion I think it is just a lame excuse to blame it on the Hungarian guy and make him the scapegoat. He might have parts, he might have boards, but it is very unlikely that one can get these alleged very special parts in Hungary only.

The hole reason given by this bushing guy why he needed to do yet another design and board sounds like bullshit to me.

They already failed with this project IMHO, and should return the money to the backers. And i guess they wont be able to do that.
 

Offline EEVblog

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Re: openvizsla......... still......
« Reply #45 on: August 02, 2013, 07:54:29 am »
They already failed with this project IMHO, and should return the money to the backers. And i guess they wont be able to do that.

He admits there is enough money left to do a new run of boards, so there is absolutely no reason why backers can't be refunded at least in part.
 

Offline mikeselectricstuff

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Re: openvizsla......... still......
« Reply #46 on: August 02, 2013, 08:52:40 am »

Agreed. Signal integrity and termination will be terrible, and probably also negotiation.


That's not it .. There is no menage-a-trois on usb , USB is point to point ! you can not have a third transceiver cell on the pair of wires. even if that transceiver would be listen only. You need to have two transceivers and basically replicate the dataflow. that means all data has to go through the fpga.

you can't simply splice the wires ...

@alm : they are using a 3340 not a 3343 ... look at the block diagram. they clearly show the switch to bring out the DP and DM to wire up to a high speed phy. the internal phy is full speed only.
I'm not familiar with  details of USB transceivers, but surely by limiting cable length to, say 1m, you can make use of the margin between the 5m cable limit and the 1m cable used to allow a passive montoring probe with non-trivial loading.

I'd have thought perhaps a better way to do this is for the monitor to pretend to be a hub, that way you avoid any loading issues.
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Offline Short Circuit

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Re: openvizsla......... still......
« Reply #47 on: August 02, 2013, 11:04:04 am »

I'd have thought perhaps a better way to do this is for the monitor to pretend to be a hub, that way you avoid any loading issues.

That is the last thing you want from an USB analyzer because a hub is an active device at protocol level also. So it screws with timings and with the enumeration process. That is not a problem with a perfect device and a perfect host running flawless drivers, but that is not what we need USB analyzers for  ^-^

For example Last time I had to dive into low-level USB debugging, the problem appeared when the device was connected to a hub, went away when connected directly to host...
 

Offline firewalker

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Re: openvizsla......... still......
« Reply #48 on: August 02, 2013, 11:06:55 am »
Apart from the sniffing /taping and the way to "wrap" the usb.

The analyzer part? What will the offer? Raw data?

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Offline kaz911

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Re: openvizsla......... still......
« Reply #49 on: August 02, 2013, 11:09:20 am »

They already failed with this project IMHO, and should return the money to the backers. And i guess they wont be able to do that.

And why should they return the money? Read the kickstarter terms - if you back something on kickstarter - YOU risk losing your money without getting anything in return. That is the clear and stated terms.

So Kickstarter is a "gambling site" - so never put in more than you can afford to loose. If it was risk free - it would not be a Kickstarter to help people lift products ' off the ground '

Less than 1 in 10 projects founded by professional investors actually turn into profitable companies. But it does seem like more than 1 in 10 projects in kickstarter turns something out to their "investors"
 


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