Well, the original reason for creating PSHDL was that I wanted to have a language which makes it easy to identify registers. My PhD Subject area is FPGA architectures and as such I wanted to have a set of benchmarks that could be used to test various architectures. The problem with VHDL and Verilog is that it is not obvious at what places registers are generated, that is if you slightly diverge from the most obvious description of something. Also parsing VHDL is a major pain in the ass. With that in mind I created PSHDL, which I then figured was significantly simpler than VHDL or Verilog. It also fixes the most common problems that I encountered when teaching VHDL in our university.
In the practical labs the students have problems to understand which parts of VHDL should be used for synthesis, and which not. The most common problems are latches and mismatches between simulation behavior and synthesis results (caused by latches, sensitivity list issues and weird descriptions). In PSHDL you simply can't create latches and the simulation will match what happens in hardware (if correct timing is ensured).
Another problem is tooling. It is very difficult to create proper tooling for a language like VHDL. This is partly due to the grammar, but also due to the ambiguous usage scenarios. The IDE can't know whether something is used for synthesis or simulation and thus provide error messages that are relevant for the user.
Also those simplifications enable a new kind of simulation. One where you can compile PSHDL to a regular sequential language (currently supported are C, Dart, Java but others like Phyton or PHP could be added rather easy). This allows you to embed the simulation into your reference implementation.
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