Professional ITIC USB 2.0 LS/FS/HS Protocol Analyzer Kickstarter Project

[sunnyhighway]

I'm currently looking into attracting professional Angel money: http://www.techcoastangels.com. They have much deeper pockets and can contribute with management and coaching too.

Could be a good choice in your case. But do keep in mind how their pockets became deep in the first place. Don't give in to their first offer and put up a serious fight for your cut. If not, you might find yourself on the short end of the deal.

[Rasz]

I cant see VC investing in a niche like that.

[John_ITIC]

I cant see VC investing in a niche like that.

An Angel is not a VC. Google will reveal the difference.

[Rasz]

I cant see VC investing in a niche like that.

An Angel is not a VC. Google will reveal the difference.

nah, its all the same. They bring money, and require stupid returns. Nobody is going to fight over niche product enabling development for _old, outdated_ standard, in a market full of competition.

well, maybe if you slapped accelerated IoT diversity empowering stickers on it.

[Precipice]

Is there any temptation to sell yourself / the product to Microchip (or some other USB silicon manufacturer)?

[John_ITIC]

Is there any temptation to sell yourself / the product to Microchip (or some other USB silicon manufacturer)?

No temptation on my part! I have also contacted a local Angel investor to see whether they understand this enough to want to get involved. Angels are essentially interested in making some 10x return on investment for low risk and this certainly applies in this case. In contrast, VCs are interested if their multimillion dollar investment can be put to work. Angels investments run in the $100K to $500K range.

I have actually now started work on a USB 3.0 Protocol Analyzer.  This will get done with or without investor involvement. Essentially, the technology is the same as my 2500A PCI Express Protocol Analyzer. USB 3.0 in fact uses PCIe 2.0 technology for the link encoding and signalling so can quite easily be built on top of the 2500A hardware (different external USB 3.0 PHYs are needed).

[all_repair]

I like this type of tools, which eevblog reader does not.  If it is for development work for a particular product, probably there would be a few on my bench already.  As it is, if time permits, maybe this can be used for hacking needs like the Novena laptop of bunnie.   Maybe I consider too much as I missed the Novena crowdfunding too, but if the Novena community builds up, it is going to be a powerful tool.  I know I am going to get a Novena sooner or later.  Maybe some repositioning can help.

[marcan]

I like this type of tools, which eevblog reader does not.  If it is for development work for a particular product, probably there would be a few on my bench already.  As it is, if time permits, maybe this can be used for hacking needs like the Novena laptop of bunnie.   Maybe I consider too much as I missed the Novena crowdfunding too, but if the Novena community builds up, it is going to be a powerful tool.  I know I am going to get a Novena sooner or later.  Maybe some repositioning can help.

FWIW, since the host side software is open source, OpenVizsla already works with the Novena (and, together with the Novena's FPGA and its high-speed interface connector, makes for a very powerful combination for reverse engineering of USB devices in a small, mobile form factor!)


(Sorry for the plug, but I just had to, considering this has been done before!)

[John_ITIC]

A quick update: Like i mentioned earlier, I have started the design work of a USB 3.0 Protocol Analyzer. It will be built around an Altera Cyclone V E, in 896 pin package (A7 device). It will have a 4 GByte DDR2 SODIMM and two TI TUSB 1310A PHYs. The idea is to pass the data through the FPGA rather than snoop on the data going by. The reasons are complex but essentially boils down to the requirement to have single ended terminators turned off when the upstream port is not powering the bus (or when the link goes into U1 low-power mode).

An additional advantage with passing the data through the FPGA is that the unit can also act as a traffic generator, BERT tester etc. In other words, the same board can be used for multiple instruments.

The form-factor will be the same as the 1480A (USB) and 2500A (PCIE) analyzers, namely a small 120x100 mm pocket-sized unit. This should be the smallest USB 3.0 Protocol Analyzer on the market.

More details as available! Of course, I won't bother crowd-sourcing this...

[marshallh]

A quick update: Like i mentioned earlier, I have started the design work of a USB 3.0 Protocol Analyzer. It will be built around an Altera Cyclone V E, in 896 pin package (A7 device). It will have a 4 GByte DDR2 SODIMM and two TI TUSB 1310A PHYs. The idea is to pass the data through the FPGA rather than snoop on the data going by. The reasons are complex but essentially boils down to the requirement to have single ended terminators turned off when the upstream port is not powering the bus (or when the link goes into U1 low-power mode).

An additional advantage with passing the data through the FPGA is that the unit can also act as a traffic generator, BERT tester etc. In other words, the same board can be used for multiple instruments.

The form-factor will be the same as the 1480A (USB) and 2500A (PCIE) analyzers, namely a small 120x100 mm pocket-sized unit. This should be the smallest USB 3.0 Protocol Analyzer on the market.

More details as available! Of course, I won't bother crowd-sourcing this...

Count me in. I won't have these other analyzers on my desk for much longer.
One of the reasons I have the Lecroy is because it does traffic generation. You can run a suite of compliance tests against the DUT, they are VBscript that talk to a Lecroy API. The whole thing is very much duct-taped together and new bugs are always being found.
If you can make it useful for preliminary compliance testing, that will be huge.
Lecroy also has many additional tests that are far more useful/informative than the USBIF ones.

You may consider using LPDDR2 instead of DDR2 so-dimms. Smaller, not expensive. A bit harder to source, but cheap DDR2 sodimms are quickly fading into the past.

[John_ITIC]

Count me in. I won't have these other analyzers on my desk for much longer.
One of the reasons I have the Lecroy is because it does traffic generation. You can run a suite of compliance tests against the DUT, they are VBscript that talk to a Lecroy API. The whole thing is very much duct-taped together and new bugs are always being found.
If you can make it useful for preliminary compliance testing, that will be huge.
Lecroy also has many additional tests that are far more useful/informative than the USBIF ones.

You may consider using LPDDR2 instead of DDR2 so-dimms. Smaller, not expensive. A bit harder to source, but cheap DDR2 sodimms are quickly fading into the past.

I did a search but could not find any LPDDR2 SODIMMs, only LPDDR3. I need to use DDR2 because Cyclone V does not support write/read-leveling required by DDR3 DIMMS. I know other USB 3 Analyzer manufacturers use higher end FPGAs so they can use DDR3 but I feel the cost is not justified. 4 GByte should be plenty. Micron still have them active and there are a ton on the open market so should not be hard to source.

I'm debating with myself whether traffic generation is worth the investment. Most people would likely use the analyzer to find bugs in the communication protocol. LeCroy has extensive traffic generation and protocol validation. So does Ellisys. I suspect it is not good to try to meet all their traffic generation features - that will result in exactly the same offering. Likely better to have the most needed basic features with a lower price?

[macgyver0815]

You could get in trouble with sourcing old DDR2 at acceptable pricing in the next few years. 

Cyclone V does support DDR3. You've got BGAs and impedance controlled PCB anyway so why not use the chips directly?

[John_ITIC]

You could get in trouble with sourcing old DDR2 at acceptable pricing in the next few years. 

Cyclone V does support DDR3. You've got BGAs and impedance controlled PCB anyway so why not use the chips directly?

I need 4 GB SODIMMs. It makes no sense to put 4GB with discrete parts on the board when SODIMMs are readily available.

[John_ITIC]

Well, as expected, little interest in the project due to much too high cost so the KS campaign yielded little interest. Thanks to all you that pledged, though.

As mentioned, I am instead working on a USB 3.0 Protocol Analyzer. I'm currently doing the layout of the PCB. Picture attached for those interested (120 x 100 mm PCB).

[marshallh]

Looks good. You can disable "Ordered blending" in ALtium PCB3d settings to get some nice antialiasing/smoothing.

[John_ITIC]

The USB 3.0 Protocol Analyzer PCB is now fully routed. I have attached a couple of 3D screenshots. This time with the Altium Designer antialiasing fully turned on to 16x. The viewing is a bit sluggish so a good trade-off turned out to be 8x while working with the PCB in 3D.

Next step is to import the PCB into Hyperlynx and do the Signal and Power Intergrity tests. I have to make sure that the DDR2 interface is working properly. Later, I will create an Altera Quartus II test design to make sure that my FPGA pin-out is valid. In the past, i incorrectly pin-swapped to invalid pins - Quartus II will catch this so i'll make sure to test properly before sending this PCB to the factory for a prototype.

This will absolutely be the smallest USB 3.0 Protocol Analyzer on the market (120x100 mm PCB). The small PCB will make the GND and PWR planes smaller so requires proper power integrity similation to ensure sufficiently low plane inductance. Making things small has interesting challenges 

/John

[Precipice]

The USB 3.0 Protocol Analyzer PCB is now fully routed. I have attached a couple of 3D screenshots.

I take it you spotted the tracks in free space over the routed bit of your edge connector?
(I tend to run a keepout line around the edge of the PCB to remind myself....)

Looks great, good stuff!

[Kean]

@Precipice - Well spotted!
@John_ITIC - Looks great.  Out of interest, how many layers is it?

[John_ITIC]

Ha! No, actually didn't see those tracks but it is fixed now

The PCB is 10 layers with blind vias. This is the minimum technology board that be used with this high ball count FPGA. Any lower than that and it can't be escape routed. As it is now, things are quite tight, routing-wise.

/John.