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VisionFive 2 kickstarter, $49 4 GB 64 bit quad core 1.5 GHz RISC-V

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--- Quote from: Nominal Animal on September 07, 2022, 09:42:49 pm ---
--- Quote from: SiliconWizard on September 07, 2022, 06:49:42 pm ---
--- Quote from: Nominal Animal on September 07, 2022, 08:21:57 am ---Vendors providing their own forks of open source projects as SDKs is a stupid, wasteful way of supporting SBCs.  We can do better.

--- End quote ---
I do not disagree with this, although I personally still don't know how to leverage open-source in a healthy business model.

--- End quote ---
With Linux SBCs, we can assume profits come from the hardware sales, so the target (for the vendor) should be to minimize maintenance cost while maximizing the user demand. (...)

--- End quote ---

Well, for this particular market, I agree completely. Actually those boards are 100% useless without proper software support, all the more that they usually come with no to very little hardware documentation and writing your own support is often not even doable.

Without Linux, they wouldn't sell a single board. So they are leveraging it and they definitely need to give back in the most open way possible.

I'm in contact with a developer in China who has a prerelease Pine64 Star64 with the same JH7110 SoC. It came running at 1.25 GHz but they've yesterday bumped it to 1.75 GHz and it happily ran stress test overnight, reaching 43 C in a room that was around 30 C. They do have a heatsink with fan on it at present, but plan to try without after the weekend.

The data sheet gives Theta-JA as 8.1 ÂșC/W (on the 1 cu foot box JESD51-2 still air test procedure, I assume), 5 W maximum consumption at 1.5 GHz, and 125 C maximum junction temperature, so it should be absolutely fine without a heatsink at all in a domestic/office environment.

This SoC is looking like being the 2nd properly-engineered RISC-V applications processor after the Allwinner D1. But the D1 is single core single-issue at 1.0 GHz, while this is quad core dual-issue (~1.6 IPC in practice) at 1.5 GHz, so up to maybe 9 times faster in aggregate.

The only slightly annoying thing is it uses the 21G1 U74 core release, which is at least a nice upgrade from the early 2019 core using in the JH7100 test chip in the VisionFive v1 (and earlier BeagleV beta board). But the 21G3 U74 core release (U74-MC coreplex really) got a 4 channel DRAM stream predictor / prefetcher. The lack of a prefetcher means the JH7110 is only doing 450 MB/s on standard memcpy while the slower CPU core D1, which has a prefetcher, does 1100 MB/s. However the JH7110 has 2 MB L2 cache, which is considerably faster than the D1's DRAM. The D1 doesn't have an L2 cache.

I've got a VF2 and it's perfectly fine for development work, if you're not doing kernel development or needing to support obscure bits of hardware but just want to test your stuff on Risc-V it's quite adequate.  The main concern with this is whether it'll be like every single other Risc-V Linux SBC ever, about six months of fixer-upper DIY install and update, six months of mostly-works but increasingly infrequent updates, and then it's abandonware as the next-big-thing SBC is prepared for release and the cycle repeats.

But if all you want to do is make sure your existing code runs on a new architecture it's good enough.


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