Author Topic: WTF am I supposed to do here? Diff pair routing and DRC clearance problems  (Read 1200 times)

0 Members and 1 Guest are viewing this topic.

Online HwAoRrDkTopic starter

  • Super Contributor
  • ***
  • Posts: 1530
  • Country: gb
For the first time I'm working on a PCB layout with PCIe differential pairs going to an M.2 socket. I'm pretty sure I've worked out all my trace widths and spacing correctly for 85 ohms impedance and set up the relevant net class parameters for the diff pairs.

The diff pairs originate from and route to 0.5 mm pitch pads, but because my clearance rule is 0.85 mm, I get a ton of DRC errors because of unavoidable/inherent violation of clearances of traces to pads, copper pour to traces, etc, etc.

I don't seem to be able to tweak any of the parameters (i.e. Clearance Details in Net Classes window) to get rid of the DRC errors. The only thing that had any effect (that of actually allowing the copper ground pour to attach to the pads at all) was setting 'SMD' to 'Copper' clearance to the pad-to-pad gap, 0.2 mm.

WTF am I supposed to do here?

Edit: oops, forgot to attach picture :-[
« Last Edit: December 22, 2023, 08:36:55 pm by HwAoRrDk »
 

Online HwAoRrDkTopic starter

  • Super Contributor
  • ***
  • Posts: 1530
  • Country: gb
Re: WTF am I supposed to do here? Diff pair routing and DRC clearance problems
« Reply #1 on: December 22, 2023, 04:35:44 am »
Oh, and one supplementary question: what should I be using for clearance around the diff pairs?

One rule of thumb I've read in several places is 5 times the trace width from the centreline of the pair. But another rule I've read says 4 times the dielectric height (i.e. thickness of PCB pre-preg?).

The former works out to be 1.04 mm (0.28*5-0.36) but the latter is 0.84 mm (0.21*4). The latter helps me more with the routing.
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf