Optical Bench REDUX: Digital Switching can have Analog Functions!

[RJSV]

...it's a little hard to see, but if you look on left column near top, is wire pair emerging from hole in column pipe.  That is for the top driver LED.  Actually, there will be two of those wire pairs for top LED, for MAIN and for Auxillary columns.  That is considered one 'quarter' section, so it's one of four (corners).
Most combinations should be able to be dialed in, but straight and simple point to point (solderless) can be quickly done, also.

   This stuff shows a bit of the independence status of inventors;. Often an inventor has to delve into these areas, like packaging, or ease of use.  Actually, I enjoy those nasty MECHANICAL issues...especially with novel looking devices!  I've done a bunch of crude-rude adjustments, to life-style, as an Inventor!
Ever have to SUE, your own lawyer ?  (Yup, and he won).

[RJSV]

   There's been other views of this 'cube' and plexiglass top bracket (holding layer #1 of the gate stacks).
Hoping there is enough transparent, for daily battery charge-ups, in the sun.  Might be easier, just use a cardboard sheet, but then I'd have to dismantle things...before putting out in SUN to charge. (I'm waiting to see, if the gates, generally, get enough light, some indirect, for complete charge. Batteries are 2/3 size and at 100 mA-hr that's a pretty pathetic full-charge.
   The 8 stacks of gates taking over 1 hour to assemble, so I almost have more work in packaging improvements needed, VS. actual functional aspects, of DtoA converter, etc.

[RJSV]

   This current picture helps describe the situation;
   The whole 'series' network, of gate stacks, will eventually settle; to an alternating 'On, Off' pattern, (observing as signals going in downward direction, thru those Solar Garden Light modules.)
Currently, my recent re-assembly of 8 columns of 7 levels each, contains AT LEAST 4 gates 'spazzing', simply meaning the charge is so low that an individual gate gets into difficulty, switching on and off at a few cycles per second.
  Right now, it's 7:30 PM  California, just sundown, and a few more minutes gets fully dark. Then, all 8 columns are expected to settle out, into the On-Off-On-Off-On pattern in the 7 gate stack, of inverting gates.
   But NOW, (tomorrow morning), I've got to disassemble the stacks, and weed out the gates that underperform, in terms of chargeable 1.5 V battery.
Many years, patience, doing Mechanical logic, got me 'climate adjusted', to tricky apparatus, (Scotch Tape and rubber bands), so, I don't mind, following EDISON's phtolomy, on invention.
   99 .1 % persperation, in my view.  But, goody, that leaves (me) some territory, to reign over...
   King of the... (fill in the blank)...  It's not so bad, life in Silicon Valley.  Except food prices, skyrocketing lately...
Lol, (you gotta laugh).

  Anyway, the simple test, down through the gate stacks, is to shine flashlight and verify that the whole stack responds...by flipping state.
So, I note the bad spots, for the morning, disassemble the stacks.  Often, it's found that most failures are of battery ' falling' out from spring contacts (due to motion shock), so a quick fix to re-seat the internal 1.2 V battery.

[RJSV]

   Turns out; I took things too far, and package structure does not let in enough light..., except maybe for a couple gates up top of each column.  Had been wondering, if that pityfull 100 mA-hr chargeable niMh battery (2/3 AAA), was the limiting factor, for each daily Solar charge cycle.
Next, should also use better transparent 'loops', in the gate stacks, for better solar gain, as each gate already hampered, by taking direct light in very slanted angle.
I'm thinking adding approx another cm to each gate to gate spacing, plus getting rid of those clear plastic loops.

[RJSV]

   Some of this project maybe better in 'Projects' section, but it's all, mostly Dodgy...
Picture showing the array of column posts; these can pass wires, up through (pipe) interior.  Right now, I've had to shorten that whole mass.  The whole package, mechanically speaking, is looking pretty good.  Those columns support the components (garden light modules), that I've termed as 'gates', plus they block some portion of unwanted direct light, going sideways from a nearby assembly.
   Expansion of the stack size gets things up to about 17 inches, (1/2 Meter) height (was ~ 14 inches).

[RJSV]

   I really would recommend the Prof. Shanlei Fan lecture (thanks ebastler):
Please see post on July 31.  Especially interesting, (at video 44:00 minutes out of 49:00), Professor Fan brings up the situation, that computer scientists DON'T KNOW, exactly, how the whole process works; it's almost like attention is on, generally, how to construct a 'problem solving' network...but without direct reference to the problem material, directly.
Almost like, by analogy, a bulldozer built to move dirt, where the designers don't, actually, move dirt themselves.

[RJSV]

Picture showing Base Unit improvements:. Idea is to have a 6-position rotary switch selecting sources, for driving a column top LED.  Various modes of series connections can be dialed in, as in Column 3 output drives Column 4 TOP.
   Picture of (Terrier) puppy included.
   Picture of Optical 'SuperComputer' base included with puppy...
  A couple of places, along each 7-segment column, has some misc. cross-over, or other inter-gate wire connections, for having flip/flop or other customized variations, such as optical logical 'OR' gate function.

[RJSV]

   I have 'half' of an idea, regarding Optical computing elements.  In this case, needing an (entirely) optically resolved Multiply and accumulate, using light beams for either digital or also analog encoding types.
An 'Accordian Bus' (or; Piano Bus), is not a new idea.
But, for non-binary encoded logic, the idea is to use a long, 100 channel bus,... that being just in empty air, with 10 copies, of the Multiply's Multicand, which is a
'5' in this example 3 X 5.  Idea is to 'bogus out' or make invalid each of the terms, 9, 7, 6, 5, 4, and 3, while leaving untouched the transmission of  2, 1, and 0'th for a valid addition, of the 5 term, three times, in this case.
The assessment of that valid/not valid stream or linear array, is done at the end, with conventional electro-optics.  My idea is to (figure out) get a way to get one beam to influence another, and without the obviously useful electronics.

[RJSV]

Keeping in mind; there's no active components until the terminus, of hopefully a long string of multiplied...that way it's still efficient to revert to electronics, or at least some active optical element.
The method uses a third parameter, in the multiply of Multiplicand and Multiplier, I'm calling the 'Facilitator'.
It's actually, functionally the opposite as each facilitator 'ON' bit will invalidate that bit position.  Each bit, in a TEN bit word, has equal weight, (uncoded), but still notated from right to left.
   So a first multiply would involve a Multiplicand, '5', that is sent into the optical network by electronics, and looks like:.  '00001 00000'.  The other number, the Multiplier '3', is originally supplied in combination, with the 'Facilitator' bits, that de-legitimize the upper bits:
So, Multiplier X 3 is input as: '11111 10000', to be added in analog form.
   Functionally, it's as if the device is ready to stamp down '9' copies, even if this instance needs only three.
So, it's a tentative addition, but also one that collects the valid / not-valid states.  Each of the copies are kept separate, as the whole set propogates (at speed of light).  At end, there needs to be an electro-optic device, that will block, or discard the 'bogus' channel-ways, before actually physical addition, or analog Summation occurs.
   For second stage, in a string or chain of multiplies, the first stage answer is in the proper format, that being a '15' with upper bits flagging bogus spots (Facilitator).
One problem is, answer consists of 100 parallel channels.  In conventional hand-multiply, the answer must get split up, with some sort of method to deal with separate digits and overflow Carey's.
   The 'Zero' term, or bus position is needed for assertive logic, but must be separated out before the analog summing (node).
So, you can see, the overall Bus effect is analog, but can be sent piece-wise, in those separate channels.  Of course, there also is (optical) decay effects, mostly in diffusers, and also a need to normalize signal strengths (actually packets of photons).

[RJSV]

The optical processing thing, here, has an interesting quality, in that you can't actually KNOW what you have...but you can keep on adding to it!
   Considered in columns, where the structure is vertical, top-down signal direction.  So the 'bogus' or non-valid columns are marked, either by higher intensity coded, or by way of parallel tracks or pathways.
Asute readers may wonder...there is no there, there as far as hard-coded answers, like how 3 X 5 gets to '15' as an answer?  The answer isn't resolved, but you CAN apply the valid terms, as analog quantities.  For absolute conversion, an A to D conversion is needed, (electronics).
   When doing most mid-range calculations, a two digit or 0-99 range works out. The qualifying 'Facilitator' flag there, applies to a whole word, in the piano-bus of ten signals.

[RJSV]

(Diagram showing partial term Summation):

   Reading as a signal set that propagates top-downward on the diagram page, is an earlier multiply;
   3 X 5.  The free-space 'BUS', or vertical lanes are read,
right-to-left, with the inhibited lanes shown also.
(Those inhibited lanes are 'permanently' there, until electronic shutter (LCD) blocks each bogus signal).

   Next, a new signal is brought into the stream, that being the result of multiply of 3 X 2 (=6).  That additional set of lumens is special case, having a same Multiplier, being also then with same column structure, of non-valid signals.
   The total then, in the analog stack, is 21 lumens, with 6 of the columns blocked.  Obviously, such an accumulator in digital form needs a range up to 200 counts, when doing a total after 2 multiplies.  The maximum would be:
   9 X 9 = 81 plus another 81, for a digital total 162, literally.  That being with using somewhat arbitrary 1 lumen 'weight' per digital count.

[RJSV]

   Here is my suggestion, for optical BUS actions:
(Also, see diagram).  The input electronics could be doing set-up, for having floating point related, partial multiplies.  For example, a 'stack' that, in series, performs     200 + (5 X 1) + (5 X2) + (5 X 3)...as for the number 1234 X 5, where you have a partial sum.
As shown in diagram, the electronics drives LEDs for each lane, in the 'facilitator' BUS format.  That is the input for the decimal Multiplier; '5'.
   The Multiplicand, and any stages of new Multiplicands, should be in the positive-logic format, being occupying 5 of the BUS conduits, by simple count (not binary coded).
   Also included in the diagram; is shown how a value like '5' can just simply be spread across the 5 different conduits, simultaneously an analog value, weight 5 (lumens) total, if consider each light flow channel as having '1 Lumen'.

   I'm thinking perhaps could fit (one) of these passive adders into 1 mm., or less?
For the column qualifying signal (BUS), that will be an associated paired, with each data term (column).  Result is a Parallel Adder, in passive optics, with conditional blocking of non-valid accumulator columns.

[RJSV]

I'm thinking something like, 10,000 separate multipliers, which could be 100 by 100 mm.
Diagram shows, a BUS having 5 lumen, and is only shown right-justified for convenience.
   The diffuser (hopefully) spreads the light out, and evenly, across 10 new 'Laneways' or light conduits or paths...
Then, that re-build word can be subject to blocking, of specific terms, mapped one-to-one.  So, for example, it is 3 X 5, then the Multiplier, '3' gets a Facilitator word:
   '1 1 1 1 1 1 0 0 0' and that flags as not-valid, the columns coorespond with; '9, 8, 7, 6, 5, and 4'.
   The re-build word, is ready to apply that, so the end result is that the full Adder occurs, but only after the electronics activates (LCD) blocking of column.
Full-Scale is 0 - 999 or 3 decimal digits.

[RJSV]

   Working with the passive computing structures is interesting and fun...
Sometimes it is useful to be able to 'recover' an ordered set of BUS signals, although when input is from LEDs you can have the driver electronics do the heavy lifting (to provide diffuse weights, across the word).
   Result is diffused across entire word ; and that way provides the input needed for a multiply.
While the amplitude value of the light beam is reduced by a factor of 10 for each piece, this variable is only introduced once, (each), in the chain of many calculations (multiply/accumulate).  So the reductions there (are not cumulative).

   Diagram rt. side shows a system of reflective 'tabs' in the BUS channel, resulting, again, in the Word-Diffuse format needed as input to passive multiply (structure).

And...Bottom of diagram shows a single conduit feeding a divergent and varied area (conduit), that results in an even response across all elements of the BUS Signal. Showing 5 elements for simplicity.

[RJSV]

   Still chewing on this latest 'improvement', gaining the ability to drop off those bad columns, and go ahead with the full summation, BEFORE resolving the valid / not-valid flagging of columns.
   It's possible to get the lateral or cross-column summation(s) done, but as a set of ten potentially valid results; each of the 10 possible final multiplications can be done, in parallel.  The signals must be split up, into 10 copies,...of course with reduced amplitude, then can be added.
Out of the 10 possible outcomes, the correct result can be distinguished, by the stack terminus electronics, and that electronic section is not required to perform the lateral additions, column to column, as the optical pathway gets to add everything, in-line.
That way the electronics function is reduced, to shutter control, or light deflector control.
In that example multiply, of 3 X 5, the 3 valid columns, col 1, 2 and 3 each contain '5' lumens (of photons flow per second), so the addition result is 15, ignoring any issues with decimal points.  The other columns in this example, do not get into the (optical) summation.
   AND, by the way, this functional gain comes with high price, as ANY structures following will need to be duplicated TEN TIMES!, to cover all contingencies.
   It's an interesting project; Digital Multiply where the words used can also be analog: An analog multiplication result, but that has synchronized or one to one mapping, with a digital signal 'Facilitator' word.
And also with unchecked analog Summation (no set word size).
Very interesting.

[RJSV]

   An electronically shuttered column set could make for a fast digit multiplier,...that is a hybrid, digital addition, but of some analog value.  I've got a somewhat arbitrary range in mind; that is zero to 1 volt.
( 3 digit decimal 000 through 999).
Suppose a fast multiply, could do X 7, on a sensor input value, with some more terms added in, to the analog total (columns merged in summation).
That could be; '(7 X 3) + (7 X 4)', where that '4' came from some brief memory device, but then a larger stream that could include; '(4 X above result of 49) for a subtotal 196.
Then, perhaps, a constant of 149 gets input, from some other nearby calculating subsection.  It has topology similar to river structure.  The electronic portion sets up the LCD shutters, ( or other, faster options), then leaves that 'transient' structure for a time, to process.
   One advantage, of the blistering optical speed, to resolve a multiply- accumulate outcome, is that any sensor signal going through separated portions, won't have any significant issues with being different (slightly) valued, and thus eliminating need for a sample and hold front end.
   Using the thousand counts range, any comparator would best be at 1/2 Volt, or 500 mV., I figure..., out of the full, 1 Volt range.
Of course, the steps are 'linear', 1 mV each, but actual optical hardware maybe only (sometimes) close.
The 1000 step range does pretty well, when accumulating up to ten multiplies (that's 810), and the subsystem allows for 'constants', like '149' to be tossed into the mix (summation, to the AtoD.)
Output would be created quite rapidly, at light speeds, for each AtoD convert, at the column set terminus.
That apparatus expected to be on order of 50 cm (tall).

[RJSV]

   Filters as sensor front-ends can illustrate the set of multiply and accumulate actions:
  This first diagram shows a typical air bourne sound being translated to light beam angle. A partial obstruction before any conversion might help provide modulation of the constant light beam.
The first cone is to concentrate the air pressure waves of the sound, onto the cone or diaphragm for variably reflecting some light beam.

[RJSV]

   The diagram shows an audio filter front end, skipping completely any electronics based parts, a typical filter or low-pass relationship can be using a short delay line technique.
   First receiving cone, directs sound pressure waves into that tube...; 12 feet long for about an audio delay of 40 milli-seconds.  The other 'signal', direct, then travels to the multiply unit, along with the 40 mSec delayed sound (that's also decayed quite a bit).

[RJSV]

   Of course, there are other, easier ways to get some ratio, like here it's 1 TO 0.5 ratio.  But here, to illustrate, the starting and ending Lumins are close enough, to allow chaining, some.
The values are input direct (currently, no delay), multiplied by 6, and a 10 mSec delayed signal, at 5 X.
Because of the divide by ten side-effect, those become
times 0.6 and 0.5...
   But the whole point is, a total 16 Lums comes in, and total 9 Lums gets output, so the chaining of stages hopefully won't bring the signal down, excessively (like ÷ by 10 would, if at each stage).
   Those values shown, cartoon style, are valid, and ready to be summed, (laterally), as the LCD shutters are blocking the columns that aren't part of the conditional addition (summation).

[RJSV]

   Going to a system, 3 by 3 dot format, allows for a 'shutter' that admits 1 through 9 total little squares of light, (or none, for zero).  It starts to look like a light diminishing filter, in various ratios of signal decay.
For multiplication, you've got a pattern, the Multiplicand, and that gets transmitted thru the tailored decay, as a ratio to 100, such as 24 / 100.
Experimenting with concept of analog BUS style, having a high digit, and a low digit, roughly equivalent to decimal digit structures, and having 'interpreted' weights, for summing purposes, while each 'digit' or decade position has similar, or non- heiracical relations...That means the actual average level of an analog channel might be same or close to other channels, while interpreted 'weight' might be as 'small character/ big character' similar to decimal 'ones/tens / hundreds' stacking
That way, the most feeble channel has strong signal, along with larger represented values, from mid-level channel.

[RJSV]

Picture Shows:
   It's ackward to get last, tenth LCD shutter element in,  that 3 by 3 array makes a nice square shape, of active 'light valve' elements.  A 'tenth' little square allows for doing a '99' output, but also a number like '52' would have a two worth of light admitting opening, supplementing the higher-weight 'tens' digit (channel).
If 10 actual pixel locations are used, then that's going to use 30 pixels across, to do the 3 squares, plus any spacing...
   One key, is that the lower represented digit is still strong; being 10 X too big, by weight.  So conversion to actual template involves reducing that, before all is merged.  That '52' being '5 regular squares', plus 2 of the little (ten times less).  Actual filter performance, for light intensity or amplitude, would be 52 out of 100 as a ratio of input to output light

[RJSV]

...This other picture features an older light panel, salvage bin now, but was inside a nice portable TV, vintage 2010.  The TV Screen back light panel is approx 8 inches wide by 3 inches high

[RJSV]

   At any rate, doing things like this, mostly motivated by the advantage of having more resolution, you could have something like;
   (Instead of just '6' X '7' type of one-digit resolution),
   149 X 52 (that's approx 7500)
For that, in a binary range of 0 thru 8196 (or 8 k), that's going to be 13 bits AtoD conversion.  So, by keeping 10 bits, converting as 0 thru 1023, or better thought of as 0 thru 999, decimal, you've got the better accuracy, 13 bits, in your accumulating light beam, with a 'truncation' of 3 bits at the final, AtoD after summation.
That helps keep rounding errors out, as the Multiply-Accumulate 'stack' has many terms, for efficiency (hopefully).

[RJSV]

Oops, sorry I jumped the gun there; it was supposed to be limited to 0-99 each,...; so that '149' is too big.

   The format cannot be sustained down the stack, but rather it is an input format.  After input, and summation that is allowed due to the shutters being closed and only open on valid columns (in the conditional summations), after that summation the BUS format must revert, to a zero through 99 type 'wide bus'.  Ironically, you can manipulate the number, sending it through yet another process...But you cannot know the value...; It's just some pile of weights, that's all been blurred and re-compartmentalized, into 10 pieces..., for any further multiply and accumulate steps.
   So, the 3-digit 000 thru 999 in the form of 'Hundreds/ Decades/ Ones', is really a format for input; as a DtoA production.

[RJSV]

   Picture features a 'wanna-be' BUS style, perhaps...if I can figure out some coherent approach.
   Idea is to have separate analog channels, one for each decade, staged much like conventional decimal numbers, X 10 for each next column.
   That 3 by 3 configuration gets you up to nine...and then you might also need another '9' set of loose digits, meaning that you would be combining 9 (X10) + small digit X1.
   It's pretty vague, right now, but has a 'Self-Similar' structure, when going down into lower weight digits / columns.