Optical Bench REDUX: Digital Switching can have Analog Functions!

[RJSV]

   For some analog fun, the diagram shows part of the Multiplying D to A Converter.
   In an example 4-bit size, the value '0101' is shown, a typical bit-weighted, shown here by area, adding up bit2 and bit0 (that's a binary '5').  To do the multiply, each of those 'ON' bits allows, instead of a constant value, allows a PWM signal, to be summed.
   This could all be done digitally, of course, (but with the garden lights as logic).
This analog method, doing a Multiplying DAC, does not mean that the PWM makes it through any of the gates, intact...it doesn't.  But it's helpful right there, at the instance, into an Optical Summing node.  In the diagram, the left side example has the PWM intensity level at approx. 30% while right side signal represents about a 50% PCM representation.
If that example is 0101b or '5' out of 15 max., then the result value, of the left side example is 1/3 of 30% or 10%.  Right side is 1/3 of 50% or about 17%.
The threshold is 0.5 Volts, in the comparator, so everything gets normalized at that kind of level.  One method, for doing small normalizing adjustments, would just simply pull the apparatus back a bit, that having a scaling and reduction effect.

[RJSV]

   This schematic includes a pad-down effect, implemented by simple distance, of emitting LED.
The digital PWM signal does make it through the enable gate, just before the attenuating, measured distance, the attenuated, or 'weighted' PWM can only have an additive effect right there, adding it's (photons)into the following optical input cell.
However, the ability to cross longer distances, without altering signal, is still available...just not in this schematic.

[RJSV]

   Here is a simple MOD; gets you an LED output pair.  In photo close-up you can see the LED was snipped out where that left a 2-pin 'header'...You can see, that 2 pin cable connector and wire, gets you a lot, for leaving the rest of the garden light intact as-is (although battery life sucks).
   LED leads actually too short to use, but it's only a few gates that get this EXT type interface.
It's convenient with FlipFlops, as the LED output can be extended around a circle type of layout.
Plus, some places need an extra, 2nd. LED.

[RJSV]

   It's a bit Ass-backwards, but the Schematic here shows the general scheme, for generating a (crude) PWM signal.  The 222 khz source on the left side of diagram providing a Charge Pump, to (right side) capacitor C1, while second gate, on right side, handles the typical voltage comparator.
The RC there, 0.1 uF X 1 kohm gives 100 uSec as a design starting point, idea being a cycle of timed pulse width every 100 uSec.
The third YX8018 'gate' module (not shown) is to provide output cut-off according to local light intensity...translated of course, by this third gate.
That's 3 compact assemblies, at a buck-20 price!
Those 3 'Garden Lights', plus a couple of 2N2222 NPN transistors for drivers.
   I might be able to share portions of this, in additional PWM generators, in other nearby logic.
   The schematic isn't finished, and, has the polarity of action probably reversed, as the circuit shown possibly gonna need a Flipflop, for start-stop control during each 100 uSec PWM interval.

[RJSV]

(Please See previous schematic diagram).
   Looking at the second gate, on the right, the usual Solar Cell has the timing CAP. replacing it; that way the little solar module is comparing for capacitor (timing ramp) voltage, for ending each 100 usec cycle period.
That will need some tweaking, and obviously the battery won't be getting (solar) charged automatically.

   Another concept: there is a way to provide an 'exponential' based ramp, by sequencing up through binary weighted values...a kind of digital generation that would sequence as 1, 2, 4, 8 etc. creating an exponential shaped output curve, (rather than integer counting linear ramp).  Actually, basic digital binary counting registers are VERY bulky, using the garden lights for optical digital functions.

[RJSV]

   I've shown parts of this before, diagram helps explain the role of conversion, analog (light intensity) to a crude PWM at 10 k samples per second.
   The upper expanded size (yellow) shows how each Flipflop is packaged as a cylinder...sometimes that could be a closed tube, having reflective inner surface.
The Flipflops each consist of 2 gates, plus that (extra) LED on the output end has been 'looped around', to face into the Flipflop cylinder input end.
   Below that slightly 'exploded' view, you can see a great big PURPLE arrow, indicating the ultimate output is the Summing Comparator (gate).  Purpose is, just like a classic style AtoD converter, to allow the sequencer to either keep or cancel the latest of the Bit weight being tested (for overflow).
   Of course, that sequencer mentioned is a whole subsystem in itself (bulky!).  The smaller view shows some of the components that might not always FIT, conveniently; that's the motivation for developing PWM methods, as that DIGITAL signal can be transported.
As I explore the practical aspects, of course that PWM excercise turns out to be pretty complex and bulky, itself.  But idea is to off-load any task that gets too bulky right in an immediate 'Analog Region' where distance and obstructions would cause uncontrolled attenuation.  The PWM channel, shown exiting that (lower right) region is thought of as a sort-of 'PWM HIGHWAY'.  It is supposed to carry an analog light intensity, over to the main comparator, without lossy issues to correct,...3-D geometry wise.
   You can also notice; (red color) the 'DtoA' portion shows 3 channels, a stronger higher bit, bit2, and another two bits, bit1 and bit0, where bit0 is the most distant, from comparator gate.
   It's fairly conventional A to D fundamentals, although the method is slightly different, in that the embedded DtoA conversion is ADDED to the value of light intensity being measured.  That way, the end result is a backwards, Two's Complement value.  That's due to using the (unmodified) fixed level sensing.

[RJSV]

   Frame and suspended rails make a cheap - stable 'wireless breadboard' (pun).
   The broadside view shows 4 channels, of an intended 8 channel Ring Counter Sequencer, for an AtoD converter.  The idea, for open frame, is for quick positioning, while having that structured approx. like I wanted; That is, having four Flipflops, in a 2 by 2 arrangement, and with 3rd layer of gates up top. 
   So the overall is 2 X 3 X 3, where the 3rd, top layer is providing a right to left signal path, then FOLDED over 180 ° (degrees) to come back, towards ultimate sequenced outputs, 1 thru 4.

[RJSV]

   Those yellow colored gates, (previous photo), are the sequencer outputs.
   In this photo, left side of gate assembly, the starting gate, of each of the 4 flipflops, is acted on, by upper layer, that is the two phases of clock needed, for the shift register, or ring counter.  Phase 1 will shift from gate 1 to copy bit to gate2.
Notice the direction change, as the upper layer shows LED outputs, phase 1 and phase 2, while lower (2X2) four are the inputs for those 'Phase clocks'.  That's via a wired extra connection, from layer3 LED Outputs.
   One main goal here, is to verify the 3-D placements.
A couple other advantages now, with frame and rails, is that a light blocking cloth towel can be easily placed over.  Also, (eventually), the gate's position can be stabilized enough...the whole apparatus can be placed in the sun, for recharging.

[RJSV]

This view, is the output array,...sorry if the frame cross member is blocking the view, of center layer of outputs, that, along with lower layer, are the 2 X 2 outputs, that go to the 4 bit example AtoD converter.  Each sequencer signal pair does first a SET, then a specific TEST, allowing gate comparator a chance to do immediate RESET, if overflow occured.
   That way, after the SAR sequence completes, the 4 bits Flipflops will hold the answer value,...a 'Two's Complement, of actual analog value, (being also added into the main summing gate.

[RJSV]

   Here is diagram, of the shifting portion, of the 4 bit shift register, used as a Ring Counter.

[RJSV]

   This 'thing' is as new, to me, as it is to READERS...
Breaking news, and all that.  The mechanicals, or the 'Fit and Function' design issues dominate the scene.
But that's OK, I have a 'keen sense' (lol), for industrial design and looks.
   That rectangular frame pops together fast, and the (red painted) 'hook rack' does OK, provides parallel rails, but I don't want all those hooks, so they will come off.  It's a bit of a test, and kind of like trying to see how many members of a BASKETBALL TEAM can you fit, into a single bed.  I'd like to see the job description for that...Something about 'fitting' a Tesla Convolution IC, into a, uh...I'm running out of descriptive language!
That's my zone,...good or bad.
   You may recall, in all this mess, that current sub-system is for doing the DtoA portion of Successive Approximation scheme; task is get eight bits all together in close proximity, and shoot that bundle of pixel-joy, into one 'Comparator' gate...along with whatever light beam is being measured.
   Odds are, I have no current competition, which can be good...or perhaps some, devious foreign or domestic SPY group is gathering up all this.
   Patent Office sees 'Novelty',...but novelty don't mow the grass.

[RJSV]

   Here is another camera angle.
Next, those unneeded hooks will be taken off, and more of the parallel rails to be added.
   The sides, of this frame, are where the outputs come out, and next module will have more logic.
Current test build, is actually an 8 output state machine style sequencer, but much of the logic looks similar, in long stringy runs, of components (gates).  But that uniformity helps here, as many of the frames can be built similar.

[RJSV]

  The enclosed photo showing, a total of 32 'gates',
just a first test, each rack lane can handle as many as eight serial-connected, (by light output).  Of course it's cheating, a bit, by relying on wires and LED extensions.
Most of the easy mods are, one is to split the two LED terminals, simply out to a pair, in parallel.
   The nice, and only moderately complicated, is the ANALOG (full, including carry) ADDER.  The left side, has output gate, in RED.

[RJSV]

   In this next, close-up (please see photo), most other gates cleared away so you can see, the extension that goes between two gates.  Right-side has yellow input gate, withe signal, plus portions of optical DtoA, also yellow.  (See also, the photo has a V shaped clip that indicates the '180° degree' turn, back to a normal right to left signal flow organization.

[RJSV]

   This photo, shows the empty segment, between two gates.  This is for the combination process, where the (next in line) rather than 'branching out' the process is analog addition, into the little solar cell itself.  Best done with wires coming in, as interior will be host to 5 LEDs, that is, an analog 'A', and analog 'B' plus a D to A  converter, equiv. to about 3 bits binary, or steps of
 12.5 % as the D to A is used, but that is usually figured as 'N-1' so 100 % is the comparator threshold, when switching happens.  Apparently, thats for a cell output voltage close to 0. 5 Volts.
   Of course, no giant expectation, of linearity there, possibly far from it.
   One thought, to maintain that 8 step intensity of LED light, in terms of resolution, is supplementing with a kind of hybrid ' upper digit'.  That would have same resolution, but in a separate analog channel, this upper digit represents, loosely, the (digital) 8 and 16 bit accumulators in 'vintage' processors.
At any rate, 3 LEDs for the Dtoa and you need 2 LEDs for the A + B, the 5 optical intensitys are summed.
If carry, then that immediate ADD is not valid, as the comparator was in 'saturation', above 100 %.
Also, a digital gate, like 3-input NOR, could use that connecting mid-way segment, as 2 or 3 signals merge into the gate's input section.

[RJSV]

Here is a better packaged Flipflop, a cross-connected standard Set /Reset.  It has fuller function, as (hope) those two intermediaries, the half-circles, should let in a lot of sunlight, while the two gates are obviously on-line, plus the photo shows signal flow is left to right and photo shows the F/f pointing into some more misc gates, (of a variety).
   These intermediate portions help continue that 'long and stringy' spaghetti structure, of the logic generally.
So the LEDs needed, would there, on the arcs, and pointing into the following gate's input (solar cell).
For the Flip/flop, the ON/OFF state reinforcing has the 2 wires from LED output, running backwards, to the back gate (red colored).

[RJSV]

This photo, of Flipflop package, shows the somewhat continuous cylinder, and then, to the right, the misc gate that gets the Flipflop output, is toppled over a bit to show the look of that half-arc piece.
Thanks

[RJSV]

   So while the openings help, while charging each little gate, in direct sunlight, that 'in-line' flip flop is Set or Reset by shining a light on either port, created by each half-circle opening, there...Red port being 'SET' while the other is 'RESET'.  The half arcs also help block a little cross-talk from nearby optical logic.

[RJSV]

Photo shows:
   That's 10 gates (signal goes left to right), with a simple frame, the straight portion has 6 gates, roughly a Flip-flop having 2 enable gates (4 total).
The round portion, maybe more 'theatrical', in this example that circular part could have the RESET getting distributed, as individual signals.  Notice, that circular portion is 1/2 up, in terms of vertical (gate) spacing.  Various options, but here I want Three vertical runs, of the open rails, going upward, stacked.
   And now, I'm facing the problem, when there's overflow, in analog adder...I'd like to move that 'Carry' out and over, with anything over 3 bits max value.
So, with Analog Full Adder, the light (intensity) could get high enough, at 0.5 Volts, to reach 150 % for example, and would lose the low value, resulting in a value of '1 ??'.  So, I need a way to subtract that 'high digit' portion, for determining the low digit.
   This High Digit channel is analog, and has typical DtoA converter, associated, at 3 bits or 8 discrete levels.  Bringing in a carry, is just a matter of introducing a '1' weight LED output, into the summing gate's square input cell.
   Having 3 levels, and also a twin structure behind this,
all total, is approx 32 gates, where a box-store 'flat' case has 48 Solar Lights.

[ebastler]

This is an interesting exploration of designing logic circuits from the ground up, using optical interactions as a different "medium" for the basic gate. Most importantly you seem to be having fun with it!

I can't see this having utility in "productive" technical applications, since obviously electronic gates offer so much higher integration, higher speed, lower power. But it could be used in a "logic building block" system for education, packaged in a similar way to the BRAUN Lectron system maybe?



It would be nice to directly see the state of each gate in a circuit one builds. But then again, you could provide the same functionality by using conventional electronic gates and putting an LED on each of the modules. Connecting the building blocks in a systematic, modular way is probably more easily achieved by electrical connections than optically?

When you mentioned that "the patent office sees novelty" in a recent post -- did you actually submit a patent application? Just curious...

[RJSV]

Thanks for question, Patent Office (in theory), can offer that bit of 'advice', as happened with myself, in so-called First Office Action.
Basically saying, examiner did a 'skim read', and found a catagory, (such as '710 Data Transfer Methods), and saw some potentially 'novel' idea(s).
   The main subject here, is to gain a 'region' I call it, meaning a 3-D space, for analog uses, where distance causes a particular 'attenuation', and electronic sensor surface becomes a 'summing node'.

Right now, photo showing, the DtoA portion, of any full adder system, where the light (going from right to left in photo) is summed, according to weight, the 3 bits being 1 of 8 levels.  Roughly representative of the built in weight network, is the distancing, first the RED LED, being the bit2, while further out is YELLOW LED, and GREEN LED, as bit1 and bit0.
For a 0.5 Volt equivalent, and linear, that's about 62 milliVolts, per step.
   You have to think in digital terms, to understand, a simple 'carry' condition, takes you to the next 'digit', but that's only an analog representation, again at 3 bits, you end up with 1 of 64, but only as a two channel analog, each at 0 to 0.5 volts range.  Point is, with a carry, into 'high digit', you simply add in another
(62 mV) worth of light, or a count of 1, in equivalent D to A terminology.

[RJSV]

To get around the parts ordering probs, I tried cutting short pieces, of regular, solderless  bread board...this being originally some 70 pins long, and with typical double-row, for IC placement, with 5 pin placements, or rather; sockets, that can take plug-in pins
So I get a set of possible 2 separate electronic circuits and battery set.  A snipped LED, and those 2 wires can act like a 2-pin header.  Then, 4 other socket pairs are avail.

[RJSV]

This photo shows paired up gates, in a cellophane wrap.

[ebastler]

Thanks for question, Patent Office (in theory), can offer that bit of 'advice', as happened with myself, in so-called First Office Action. Basically saying, examiner did a 'skim read', and found a catagory, (such as '710 Data Transfer Methods), and saw some potentially 'novel' idea(s).

But doesn't that mean filing a proper patent application, and then waiting for about 18 months or whatever the current "pendency" of a first USPTO office action is? Sure, filing an application is not expensive. But after 18 months your application will already be published, and you will also have to decide about international patent filings if it's an idea with serious promise.

  The main subject here, is to gain a 'region' I call it, meaning a 3-D space, for analog uses, where distance causes a particular 'attenuation', and electronic sensor surface becomes a 'summing node'.

Right now, photo showing, the DtoA portion, of any full adder system, where the light (going from right to left in photo) is summed, according to weight, the 3 bits being 1 of 8 levels.  Roughly representative of the built in weight network, is the distancing, first the RED LED, being the bit2, while further out is YELLOW LED, and GREEN LED, as bit1 and bit0.
For a 0.5 Volt equivalent, and linear, that's about 62 milliVolts, per step.
   You have to think in digital terms, to understand, a simple 'carry' condition, takes you to the next 'digit', but that's only an analog representation, again at 3 bits, you end up with 1 of 64, but only as a two channel analog, each at 0 to 0.5 volts range.  Point is, with a carry, into 'high digit', you simply add in another
(62 mV) worth of light, or a count of 1, in equivalent D to A terminology.

Again, it seems that for a practical implementation it would be much easier to do this with currents and voltages rather than light? Adders with current summing junctions have been used in analog computers forever, and have a much larger dynamic range than what you can achieve optically, I think. And if you want to obtain a reasonably well-working optical adder, you will have to put it into a dark box; so you even lose the didactic benefit of being able to directly see the states.

I still struggle to see the technical benefit. Doing it for your own education and entertainment is, of course, a perfectly viable reason for doing it! 

[RJSV]

Yeah, a 95¢ cent Processor IC could do everything that 'benchtop' maze could do...that's why I try not to get sucked in, to conventional electronics, like wired-in LEDs that, essentially make it more component wired to component.  (I'd like to be able to do some processes, in the spaces 'between').
Right now, working on specifics of accumulating larger values, having, for example, 3 channels, each having weighted value 8X the previous 'digit'.  At that point, those 3 separate analog channels don't have a direct link, to the physical (optical) intensity, but rather are more abstract 'just a number value', but at max would represent some 32 Volts !
That's figured as (D X 64) + (D X + D.
Edit: (D3 X 64) + (D2 X + D1
This editor keeps substituting emoji supposed to be X 8 'times 8'

That refers to having 3 bits worth of accuracy / resolution, for each 'digit''s channel.
   At any rate, I wanted some system that could do the long 'Multiply and Accumulate' terms, needed in convolution, in this case can easily sum up to 64 terms before overflowing the register.  This accumulation must be done in-line, as there is no on going storage.
I'm also hoping any PWM generation can have decent resolution, of signal output.