Author Topic: Milling layer and DRC  (Read 2227 times)

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Offline vini_i

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Milling layer and DRC
« on: April 23, 2015, 03:11:42 pm »
A team member and i are working on updating an existing board. Unfortunately the gentleman that originally created the board is no longer on the team.

Both my team member and i had finished our revisions and were days away from sending the board out to fab. I was tiding up the silk screen and to fine tune things i like to upload the board file to OSHpark. i'm looking over the silk screen and i find that the board has 4 big holes in it. i start investigating and find that two parts need board cutouts that neither i nor the other team member were aware of and we both have things run in those areas. i found the holes in the Milling(46) layer.

what perturbed me is that there were no warning sines that something was wrong. the DRC did not flag anything. the ground pours were not pulled back from the openings. nothing. if i hadn't looked at the board in OSHpark we would have made paper weights.

should those cutouts be moved to the dimension layer or are they correctly on the milling layer?
i'm using a DRC file that was made for OSHpark specifically, can something be enabled to catch if something is in the milling layer?
is there anything that i'm missing? because even looking in the gerber files we generated for Advance Circuits the holes were not there.

Offline kizzap

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Re: Milling layer and DRC
« Reply #1 on: April 25, 2015, 04:05:42 am »
It depends on the fab company as to where they want the milling information.

As for Eagle not picking up the error in a DRC check, I just checked it myself, and that does seem a little  :wtf: about it. I guess this is one of the things that Eagle needs to correct in some manner.
<MatCat> The thing with aircraft is murphy loves to hang out with them
<Baljem> hey, you're the one who apparently pronounces FPGA 'fuhpugger'

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