Author Topic: Laying out PCB without SCH schematic but with using Netlist, possible?  (Read 3196 times)

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Offline mj3452Topic starter

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Can one work like so, with EAGLE?
I mean, without schematic entry, but
design entry using text editor to some kind of netlist file.
and have back-annotation working between netlist and pcb layout?

edit: and maybe using the eagle part libraries, which do have the sch symbols?
Or then, without part libraries, but only with using package pin numbers and signal net names?

more: Text only design entry could be useful and I think, understandable, with bussed microprocessor circuits. I once built a 8031 'system' on vero board using the author's text description of the circuit.

« Last Edit: November 18, 2020, 03:35:27 pm by mj3452 »

Offline Doctorandus_P

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Any PCB program that can work with netlist files in readable ascii can be made to work this way.
So eagle probably too. (Long time ago I needed a new PCB program, did not like Eagles library structure and decided on KiCad myself).

I think back-annotation is overrated. It's a very small portion of the whole PCB design in the fist place, and using the normal workflow of updating the schematic (euhm netlist) and re-reading it with the PCB program again is just as easy.

KiCad also has a lot of side-projects that sprung up around it. One of them (there are 60+) is SKiDL.
SKiDL is a python library that helps with creating a KiCad compatible netlist directly from python.
For example, you start with declaring a capacitor and fill in some values such as the capacitor value itself and a footprint link.
Then you define some nets and give them names.

If you then decide you need a lot of decoupling capacitors, you can write a simple for loop, and easily create as many of those capacitors.
And at the end you call a library function to output the netlist.

When I was looking into SKiDL, I got the Idea it was a sort of VHDL for PCB connections, and I think that is also the way it started.
When you see schematics with big FPGA's, then you may recognize it does not make much sense to make a traditional sort of schematic for it.
It's just rows and rows of breakout pins that go to labels, that disappear onto some other page.

And, of course, the SKiDL project is an open source project, and because it's python it's quite easily readable and modifiable.
It should not be too difficult to add an option to output a (text based) netlist in a format that can be read by another program (such as eagle).

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