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Electronics => PCB/EDA/CAD => Eagle => Topic started by: JacquesBBB on September 26, 2015, 09:38:45 am

Title: How to avoid many DRC width errors when panelizing ?
Post by: JacquesBBB on September 26, 2015, 09:38:45 am

Dear All,

I am trying to cramp as much design I can in a 100mmx100mm PCB  to reduce costs.
I have properly made  each  design with no  DRC errors,
and then used the panelized ulp procedure to made the designs adequate for panelizing.

But when I import several on them in my 100mmx100mm  new board design,
I got a huge amount of width errors, whatever the option I take.

Can you help ?

Thanks

Title: Re: How to avoid many DRC width errors when panelizing ?
Post by: Karel on September 27, 2015, 01:48:17 pm

You'll get more and better help if you post your questions in the official Cadsoft Eagle forum: http://www.element14.com/community/community/cadsoft_eagle/forums/ (http://www.element14.com/community/community/cadsoft_eagle/forums/)

Title: Re: How to avoid many DRC width errors when panelizing ?
Post by: kizzap on October 02, 2015, 10:59:26 am

What are the DRC errors? there can be quite a few...

Common ones are net names, being the same, or part names being the same.
otherwise it may have something to do with the DRC rule setup not being correct.

Title: Re: How to avoid many DRC width errors when panelizing ?
Post by: matseng on October 02, 2015, 12:09:15 pm

Net names and stuff like that are ERC errors, not DRC....

OP said width errors - I guess that he failed to load the .dru file for the panelized board. The default dru have much larger min-widths than the common cheap fab houses.

Title: Re: How to avoid many DRC width errors when panelizing ?
Post by: JacquesBBB on October 11, 2015, 05:56:53 pm

I had not much help from the Eagle forum.

There is something I  still do not understand. The error are width errors.

I have set up each individual circuit board with a given .dru that gathered my setups.
I had then no errors.
Then I gathered several circuit in a single board with the same .dru file for the DRC setting.
Each time I added a  circuit, I verified  the DRC. I had no errors, except on one
where I had dozens of  width errors.

I did not understand, and
I finally send the  gerber files despite these errors.