EDA > Eagle

[Solved] PTH not connecting to inner layer pours

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Styno:
Anybody knows why plated through holes - that have the same net name as the inner layers pours - are not connected to the inner pours them when doing a ratsnest?

This is with a four layer board with a gnd and vcc plane on the two inner layers: (1+2*15+16) and using the Aisler 4-layer design rules. Any via with gnd or vcc is properly connected but none of the gnd/vcc pth’s. This happened with standard footprints like pinheaders but also with footprints I made myself, e.g. a Keystone AA battery holder.

I did not notice this during design (no DRC errors) and the Gerber review but only when the pcb’s came back and didn’t work...fortunately this is pretty easy to patch on a prototype this with some wires.

Styno:
The problem happened because the selected DRU file was missing, placing a copy back solved it. It would be nice if Eagle gives an alert when it can't load the DRU file.

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