2-layer power routing... am i going to have issues with this?

[MWP]

Greetings all,

I'm trying to avoid moving up to a 4-layer board if i can.
This is quite a compact board, which hosts a STM32F7 micro.

Below is the best routing ive been able to come up with.
The 3.3V supply traces are highlighted.

Does any one think this power routing will be an issue?

Thanks in advance

[T3sl4co1l]

I'm more concerned about ground than VCC. No pour, or is it hidden?

Tim

[MWP]

Oh, yeah the ground pour on both top and bottom layers are hidden in that screenshot.

[Koen]

The capacitor after the 3V output pin has no effect on the blue track above it, the track split should be after the capacitor.

The capacitor at the very top with a thin track to 3V has no effect either, it should be on the track before the split.

The STM32 has VDD/VSS and VCAP/VSS paired pins making it easy to directly tie VSS to the bypass capacitors GND then later to the ground plane. Attached a pic to clear this up.

[MWP]

Thanks for that Koen.

Ive made a few changes.
I cant do anything elso about de-coupling that middle bottom supply pin on the STM32. There just isnt enough room there to fit another cap in.

[AndyC_772]

Without solid power and ground planes, you have no effective decoupling above 100-200 MHz.

Does this board just have to work as a one-off, or does it need to pass EMC?

Is your microcontroller driving any capacitive loads?

[jdraughn]

Would be much easier to see if you took a screenshot without the grid.

[MWP]

Thanks for the continuing replies/help

No, this board will not have to meet/pass any EMC testing.
The only high'ish frequency IO is to the LCD panel, and SD card.

Attached is the board with filled ground planes (ground both sides).

[MWP]

And bottom layer.

[T3sl4co1l]

Top side, fine pitch SMD/SIP footprint, 12th pin from bottom: there's a ground fill inbetween traces, with no via(s) in it, and with too fine a neck (I normally set polys to 10 mil clearance and 10 mil min neck size, but here it looks finer than your other traces besides).

I see very little ground filling above or below any of those routes/footprints, which is made very difficult by the presence of rows of pins on both top and bottom -- there's no room for ground to fill around either.

Ideally, you should have ground beneath anything on top, or above anything below, and stitched around.  Any place you have traces and footprints occupying both sides, no ground can fill in, and signal quality suffers.

Just for pushing voltage around, it's probably fine, but beware if you have fast risetimes (which is typical for the outputs of most any MCU or SPI or other device), you can very easily get overshoot, ground bounce, crosstalk, clock glitches...  A good treatment is to source terminate logic pins, by adding a resistor (33 ohms or more).  Smaller values prevent ringing, larger values reduce the risetime.

Remember, only use as much bandwidth (or rise time) as you need.  For the same reason, don't forget to filter (and usually ESD protect, as well) external connections, etc.

Tim

[andre_teprom]

At the bottom layer there are some small components and tracks too close to the mounting hole. If the PCB is planned to be fixed by screws to the equipment chassis, there is a chance to the screwdriver hit this area, damaging it.