4 layer PCB - is it a good choice?

[tiger80]

Hi
I'm designing a PCB for my car (watch + thermometer, ATmega32A). I'm wondering if it's worth making a 4-layer PCB for such a simple electronic circuit: signal - gnd - vcc - signal?
Or is it better to make a 2-layer PCB and pour GND plygons on both layers and connect them with multiple vias?

I've attached my 4-layer PCB design. The TOP layer is signal, the inner layer is GND and Vcc on the entire board, and the BOTTOM layer is signal.

What do you think?

Can the VCC layer be poured over the entire PCB?

[Psi]

More layers is better in almost all cases. it makes layout easier/faster, it gives you much much better grounding with less Vdrop on VCC and GND connections, it reduces RF radiation and makes EMC better etc..

The main reason to use less layers is cost. If you can afford 4 layer it will make your life easier and reduce the likelihood of some problems occurring.

For pouring copper on top/bot layers, use GND unless you have a valid reason to use something else.
Normally with any pcb the copper fill is GND on both sides, VCC is routed by normal tracks or an inner layer.
It's not wrong to pour VCC as a outer layer, just non-standard, so it can confuse people debugging your PCB in the future since you normally assume the fill is gnd.

[Whales]

Go for 4 layer unless there is a very specific reason you need 2 layer.  4 is faster to design with, easier to design with, gives you better signal integrity and reduces EMI.   The cost increase is usually minor.

signal - gnd - vcc - signal?

Yes that's the most common choice. 

Can the VCC layer be poured over the entire PCB?

For the internal layers or outer layers?

Internal: yes, very common.
External: yes, but uncommon, and probably won't help much.

If you have the mindset of 2 layer boards then you will think you need to scrounge every spare bit of copper to improve performance, so lots of pour/fill and vias.  For 4 layer boards this extra stuff typically doesn't help that much, unless you have specific localised problems to deal with like high power loads.  Having an unbroken ground or VCC plane only 0.2mm below from your signal wires is an effective emissions control method, because the electric field will want to stay mostly confined between these two things.  Adding pour to the outer layers, next to the signal wires, typically has a smaller impact than this.

[Doctorandus_P]

signal - gnd - vcc - signal?

Yes that's the most common choice. 

Yes it's common, but not necessarily the best layer stackup. Apparently it's better to use:

(Signal + Power), GND, GND, (Signal + Power). Reason is that prepreg is much thinner (approx 0.1mm) then the core (approx. 1.3mm) on a 4-layer PCB, and it's close proximity results in better shielding.

And then combine it with stitching the GND planes together close to any area where a via changes the reference signal from the top to the bottom layer (or the other way around). This is to keep the impedance for the return current as low as possible. For the return current, any frequency content above a few kHz the lowest impedance is determined by loop inductance, and not by DC resistance. If you look around on youtube you can find a bunch of good video's with Field solvers (FEM) analysis of how the GND currents flow. Robert Feranec has done some video's about this.

And for the rest, it's a bit of a tradeoff. 2 layer PCB's are cheaper, especially for prototypes. Once you get into batches of around 100 PCB's the difference is quite small. Quite often a good 2 layer PCB can be designed, but it must be bigger (which also makes it more expensive) and it costs more time to develop. For hobbyists EMC concerns is not such a big issue, but if you want to sell your products, then I'd also be more inclined towards 4 layer PCB. Electronics also gets faster. The clock rate does not matter much, but the risetime of signals is important. For the older generations 8-bit uC boards, then 2-layer PCB's is usually quite doable. 32 bit uC's often have slew rate control for their pins. For a mixed design, for example an uC with an integrated12+ bit ADC, I'd also be inclined to use a 4 layer stackup.

You can put the GND planes on the outside, and put the tracks on the inner layers, but this will reduce performance, because you need much more holes in your GND planes. All the pads for IC's and passives create holes in the GND plane.

Putting sensitive signals on an inner layer can also be a good alternative to guard rings.

[tiger80]

Thank you all very much for your valuable information. I'm watching Robert Feranec on YouTube.
I only make PCBs as a hobby, never for sale.
I've never made a 4-layer PCB before, that's why I asked you.
Please take a look again at my 4-layer PCB design from my first post. Are the decoupling capacitors for the Atmega32 - C5, C6, C1, and C10 - placed correctly? Will there be no ground loops? The trace width from the capacitors to the Atmega pins is 16mil. The via diameter is 23mil.
I poured the inner layers: BND and VCC over the entire surface of the PCB - I'm not sure if pouring VCC over the entire PCB is a good idea.
I make PCBs using JLCPCB. For this PCB, I set a core diameter of 1.065 mm and a prepreg of 0.2104 mm. I hope the vias will connect all 4 layers.

[Kean]

The main disadvantage to 4 (or more) layer PCBs apart from the cost is that it can make it very difficult to do rework or fix mistakes.  Putting a power plane other than GND on inner layers also make access to that for modifications very difficult.

In the case of your PCB, the decoupling capacitors look file.
It looks like there is very little on the bottom layer, so I would probably suggest moving the VCC connections to traces on the bottom layer, and making both internal layers GND.

One other thing I noticed is that the through hole buzzer pads do not appear to have any copper pullback on the inner layers.  Other through hole pads show a black circle surrounding them, but these don't.

I did recently do a quick design with 4 layers, but I got the layer definitions wrong which meant that vias from an inner to outer layer didn't get drilled and plated, but vias through all layers were fine.  Took me a while to track that down, but it only affected about seven traces so I was able to fix it to confirm everything else was OK until new PCBs arrived.

[Doctorandus_P]

One other thing I noticed is that the through hole buzzer pads do not appear to have any copper pullback on the inner layers.  Other through hole pads show a black circle surrounding them, but these don't.

I assume this is about SG1? That does have a thermal relief on the left pad and a track on the right pad, but the clearance to the inner layers is obscured a bit by the green pads (I assume that is on another layer, mabye the bottom?)

Are the decoupling capacitors for the Atmega32 - C5, C6, C1, and C10 - placed correctly?

It's a bit of a nuisance to go back to viewing the PCB while this editing window is open, but an Atmega32 is "pretty old technology" and decoupling is not so critical. I did see a few capacitors pretty close to the uC pins and I assumed those were the decoupling capacitors, so that's probably OK.

Will there be no ground loops?

When everything is connected to the GND zone then there is no worry about ground loops. A single big GND zone is simply the best you can ever do on any normal PCB.

I poured the inner layers: BND and VCC over the entire surface of the PCB - I'm not sure if pouring VCC over the entire PCB is a good idea.

You may want to revise that thought when you have seen Robert Feranec's simulations and argumentation of how ground return currents flow on a PCB.

I make PCBs using JLCPCB. For this PCB, I set a core diameter of 1.065 mm and a prepreg of 0.2104 mm. I hope the vias will connect all 4 layers.

That looks about right (Core + 2x prepreg + 4x copper) for an 1.6mm (standard thickness) PCB.

[Smokey]

Because the Chinese pcb manufacturers (JLCPCB, PCBWay, Etc) subsidize small prototype quantities it is essentially always better to use 4 layer PCBs for anything you are making as a hobby or only expect to make a small quantity of.  The cost difference is insignificant compared to the design/layout benefits (and time savings of trying to optimize/cram something into a 2 layer board).

Only reason to make 2 layer boards these days is if you plan on making a huge number of them, and you are certain it will actually work on 2 layers.

[Kean]

One other thing I noticed is that the through hole buzzer pads do not appear to have any copper pullback on the inner layers.  Other through hole pads show a black circle surrounding them, but these don't.

I assume this is about SG1? That does have a thermal relief on the left pad and a track on the right pad, but the clearance to the inner layers is obscured a bit by the green pads (I assume that is on another layer, mabye the bottom?)

Yes, probably fine as the outer layer pads on SG1 are just huge compared to details on the inner layers.  It just stood out when all the other similar but smaller pads had visible inner layer clearance.

[daisizhou]

Can you share your design and open source it?

[Pseudobyte]

I think nowadays you can get 6 layer boards for about the same price as 4 layer boards.

I just ordered some from JLCPCB with their $2, 6 layer board, 50x50 deal. I know they are probably just trying to maximize panel utilization with the promo on small boards, but i will take what i can get.

Stackup of choice lately has been:

Sig/pwr
pp
GND
core
Sig/pwr
pp
GND
core
Sig/pwr
pp
GND

or if you have a double sided board

Sig/pwr
pp
GND
core
Sig/pwr
pp
GND
core
GND
pp
Sig/pwr

This works out great because each Sig/pwr layer gets great coupling to a reference/ground layer.

[tiger80]

I generated the Gerber files and it appears that the layers are connected vias. I've attached a screenshot of the top, VCC, GND, and bottom layers, as well as the vias. How can I verify that JLCPCB connects the individual layers with vias so that the VCC and GND layers are connected to the top in the correct places?

[Doctorandus_P]

I would not worry too much about via's. They are a very standard PCB feature. I don't know What PCB software you are using, but running DRC should give you quite a lot of confidence that the connectivity is OK. As a part of the Gerber files there are usually also two drill files. One for PTH, and one for NPTH, and the drills for your vias must be in the file for the plated holes. (But maybe all holes can be combined in a single drill file?)

I would be more concerned about the footprints.There are many different footprints, and some do look very similar to each other. For example some packages can have a pitch of either 0.6mm or 0.635mm. You can barely see the difference, but it makes soldering an IC quite difficult if the footprint is wrong. Some of your capacitors appear to have a "non standard" footprint shape. Are you sure those footprints are correct? Another common check is to verify whether the symbol to footprint pin mapping is correct. Especially if you are using "unverified" libraries that are created by someone else. Mistakes in library parts are unfortunately quite common.

[Feynman]

Are you soldering the components yourself by hand? A lot of vias attached to either the GND oder VCC plane don't have thermals. It might be difficult to properly solder some of your joints as the planes will suck away the heat from your soldering iron.

[tiger80]

I would not worry too much about via's. They are a very standard PCB feature. I don't know What PCB software you are using, but running DRC should give you quite a lot of confidence that the connectivity is OK. As a part of the Gerber files there are usually also two drill files. One for PTH, and one for NPTH, and the drills for your vias must be in the file for the plated holes. (But maybe all holes can be combined in a single drill file?)

I would be more concerned about the footprints.There are many different footprints, and some do look very similar to each other. For example some packages can have a pitch of either 0.6mm or 0.635mm. You can barely see the difference, but it makes soldering an IC quite difficult if the footprint is wrong. Some of your capacitors appear to have a "non standard" footprint shape. Are you sure those footprints are correct? Another common check is to verify whether the symbol to footprint pin mapping is correct. Especially if you are using "unverified" libraries that are created by someone else. Mistakes in library parts are unfortunately quite common.

I'm designing a PCB in Eagle. What should I check in DRC?

As for the components, their libraries are fine. They've been tested and used for years. My only concern is the vias, whether the connections between the VCC and GND layers will actually connect to each other with the top.
I generate Gerber files using a CAM file provided by JLCPCB RS-274X. The via file I generated is an .xln file.
See the screenshot of the CAM processor.

If the Excellon drill file is set up as shown in the screenshot, will all the layers be connected to each other in the correct locations? Or just the bottom and top layers? I don't understand this.

[tiger80]

Are you soldering the components yourself by hand? A lot of vias attached to either the GND oder VCC plane don't have thermals. It might be difficult to properly solder some of your joints as the planes will suck away the heat from your soldering iron.

Yes, I hand solder everything.

[Kean]

I'm designing a PCB in Eagle. What should I check in DRC?

JLC used to publish some Eagle DRC files available for download that had their typical 2 & 4 layer rules pre-configured.  I couldn't find them, but there are some user generated ones you can find on github.

I'd suggest you review their blog post about running DRC and ask any question you have about it.  https://jlcpcb.com/blog/how-to-run-a-design-rule-check-for-your-pcbs

If the Excellon drill file is set up as shown in the screenshot, will all the layers be connected to each other in the correct locations? Or just the bottom and top layers? I don't understand this.

As mentioned, there are two possible drill files - one for plated, and one for non-plated holes.  The former are done early in the fabrication process, and any drilled holes with copper up to the edge of the hole will get plated across all layers.  The non-plated holes are drilled as one of the final stages after all the plating steps are done.  It can get more complex when considering blind or buried vias, but that is more advanced and not something you need to worry about for now.

In the layer screenshots you posted, you can see that your vias have copper immediately surrounding them and the drill holes are marked as a different colour dot.  Vias that skip a layer (e.g. GND and VCC vias) will show some clearance so they don't connect where they shouldn't.  This all looks normal and will be fabricated fine.  You can also check this again in the preview when you upload the files for ordering, in both 2D and 3D views.

In the case where I screwed up as mentioned above, I didn't define the layers properly so there was no data in the drill file for vias that didn't go between the outer layers.  So top to bottom was fine, but top to inner layer was not.  If I wasn't in a rush and had looked at the file for more than a minute I am sure I would have noticed.  I was a little surprised that JLC didn't notice, as they often come back to me asking questions about trivial things that are fine - but I guess it isn't something easily picked up from the Gerber data (vs original design data).

[tiger80]

Thank you
Right now, I see in the Gerber files that where the via bypasses the inner layer, it has a halo around it. So it would appear to be OK.
How did you define these inner layers? What does this definition involve?

[Kean]

Right now, I see in the Gerber files that where the via bypasses the inner layer, it has a halo around it. So it would appear to be OK.
How did you define these inner layers? What does this definition involve?

Yes, the "halo" is clearance when that via doesn't connect on that layer.  Just as important is that the ones your intent to connect don't have the halo.
Your ground/power planes can become "Swiss cheese" with lots of unconnected vias.

Your PCB layers are defined in Eagle DRC settings.  You must have changed them to set your design to 4 layers.

https://www.autodesk.com/products/fusion-360/blog/every-layer-explained-autodesk-eagle/

A typical 2-layer definition is: (1*16)
A typical 4-layer definition is: (1+2*15+16)
A typical 6-layer definition is: (1+2*3+14*15+16)

See JLC standard stackups at https://jlcpcb.com/impedance

If you use the wrong layer definitions you can get into problems with via connections.  I think I mistakenly entered ((1+2)*(15+16)) and some via holes didn't get drilled.

OSH Park provide some default DRC rule files, but before you change anything make sure to make a backup of your files, or at least export your existing DRC settings before making changes.

https://docs.oshpark.com/design-tools/eagle/design-rules-files/

The .dru files are text so you can compare them easily.

[tiger80]

I have exactly what he wrote: (1+2*15+16)