1:42:15 I assume when he's saying "it wasn't a five minute operation" it took several days, otherwise why, like, why mention it, why even remember it from >20 years ago..?
I mean, for my part at least, I hardly remember what boards I did five or ten years ago. I have to look up the files to remember what all's on a thing, and that's if I've even remembered the right project...
Note he doesn't explain ANYTHING about the environment -- just that there was some board, somewhere, somehow, and swapping around the layers this way, solved it. It fills time in a talk, but it's not real useful advice -- EMC is a holistic problem space, and cannot be approached on an individual-item basis, not without justification of it.
Some possible facts he's glossed over might include:
- Plastic enclosure
- Metallic enclosure but with unusual (especially EM-unfriendly) design, effectively acting as antenna
- Unusual standards e.g. electric near-field or TEM cell
- Strict standards e.g. MIL-STD for SIGINT purposes
- Circuit and layout details e.g. number and placement of bypass caps, ferrite beads, etc.
To be clear, there are plenty of situations where such an arrangement can be a problem, and where those problems are solved with this solution; there are also situations where it has little effect, or even makes things worse.
The couple minutes leading up to this are similarly undefined: the distance between planes, and radius of field effect, are wholly arbitrary conditions. Between planes, the incident field from a via spreads out radially, inverse with distance -- at what point is it zero? Never! We might only care that it expands to a certain point, that point corresponding to some threshold amplitude, below which we don't care, it's just background noise. Maybe that's some 10s mV, maybe ~uV. And since it expands inverse with distance, we can take that distance as a ratio to via or plane clearance diameter, or plane spacing, and figure some amount of attenuation due to that geometric factor. Maybe that's some inches as he suggests, maybe it's less than a via diameter (completely irrelevant).
He does at least close that section by noting it might matter for extremely sensitive analog applications. In other words, there's, I don't know, microvolts in the gap? It should actually be quite a bit more than that, like the ~1ns edges from some LVCMOS devices (e.g. MCU, FPGA) might tend to cause some ~mV in the plane areas where those image currents flow. Still irrelevant for digital signal quality purposes (as usual: assuming jitter isn't a concern), and can be avoided by simply not routing your dirty digital power over the sensitive analog section.
The important thing is to think about these relationships, quantitatively. What ratios of signal and noise levels should you expect, given via, plane spacing, plane width/length dimensions, signal risetime, etc., and how does that compare to the required noise floor?
One more thing: not only did it presumably take them some time to complete the reroute -- he notes it took some massaging to get the internal pours to connect. That's especially chilling, and that I think is where the "even makes things worse" I said above, comes in.
Consider what that routing must've looked like. The outer layers are stuffed full of components and pours. Every single non-ground pin has a via hanging off it. For fine-pitch components, this turns all four planes to Swiss cheese, cut straight through by the rows of vias. (I think we can assume thru-vias, since he said this was a cost-critical design.) Even if you stagger them, you end up with mesh patterns (= higher plane impedance, more leakage between layers) that can only route one or two traces between a gap, and every trace you squeeze through specifically excludes power from pouring there. It's not obvious if they were able to stitch the internal power planes; whether this was an oversight, or a limitation of board area (the biggest reason I don't like pouring outer copper on high density designs, is because it's such a PITA to stitch, trying to find any unrouted opening through all 4+ layers to stick a via into!), isn't said.
And so, all of these effects combined: the severely cut-up power pours, the GND pours full of holes, the added inductance to pours due to thin and long sections -- it could well end up that some components malfunction outright due to insufficient power quality (PDN (power distribution network) fail), or emit excessive noise by the same reason (e.g. logic lines feeding cables, which when in logic-high state, couple supply noise directly into that cable). For an experienced designer, these are problems that can be managed -- budget allowing -- but it is absolutely not what I would encourage a beginner to tackle!
Similarly for the 4/6 layer comparison at 1:48:00 ish -- absolutely, more planes gets lower impedance; but does that even matter? MCUs won't care. FPGAs or application CPUs of more than small size, you probably need the extra layers anyway for routing. And, if you're willing to take the time to route and stitch pours across multiple layers -- absolutely, it will perform better, but is it worth the time required?
Other thoughts:
Probably covered earlier in the video, but to say for those reading:
The basic mechanism for a 4-layer inner-planes design to radiate from its planes, is as an extremely short, extremely thick dipole. Imagine a dipole antenna with wire diameter equal to board dimensions, and wire length equal to board thickness (say, averaged with component height, too). It's the inverse situation of the capacitor within; there's fringing field all around the edges, and less and less on the middle of the faces, or at a distance; it's a pretty shitty antenna, but this mode does indeed still exist, and it'll lead to radiation at suitable frequencies, given enough amplitude inside.
So, for most commercial purposes, where frequencies under 1GHz are the concern, the limiting levels are ca. 40dBuV/m, the board is like say 0.1m across, and amplitudes within the board are ca. 0-20dBmV (i.e. 1-10mV, typical supply ripple levels; this would be pretty intense for ripple induced by digital loads I'd say, likely indicative of needing more bypass caps -- but stick with this for sake of argument, as a worst case figure), then you need something like 40dB attenuation between in-board voltages and external electric fields (per m). Which, probably a lot of that already comes by geometric factors -- this is an electrically-short structure so it has very little gain (but, increasing with frequency), and the receive antenna is at modest distance too (3m, 10m, whatever).
If you have noisy planes -- well, why are you putting all that noise into them in the first place? You can identify individual sources and isolate them, whether on their own local planes (with whatever bypass is needed to manage them), and couple that to the main supply through filtering inductors. (Avoid ferrite beads here, as they saturate under DC bias -- they can be used, but check how much their value decreases at expected load -- that's the real hard part, almost no one provides these characteristics!) Or if it's a few particularly noisy traces, how about shielding them, you could route on an inner layer and pour GND/VCC over it just locally so the rest of the board doesn't mind, and you've not given up too much layout area to this priority route.
Keep in mind also, the problem of mistaken attribution. It's very rare that we get a chance to roll multiple versions of a design, let alone test them all. I've only done that once as a matter of fact, and it was just a little carrier board for a PSU module. (Conclusion: comparing e.g. XP ECL10US09-T vs. XP EML15US09-E, the medical version is a good 15-20dB better, out of the box, though still not good enough to meet, I think it was CISPR 22 class B; best results require a common mode choke on the secondary side, we used 100uH -- in addition to pri-sec 'Y' capacitance and a primary side CMC of some mH. This was an application with enough secondary-side wiring length, or earthing, that the PSU's claimed EMC performance was most definitely not met.) It's also rare that you'll only do one layout change (minor or major, as the case may be) per rev; you're adding and moving bypass caps, filter chokes/beads, shoving around components, filtering connectors, anything you can throw at the test to get it to pass -- and rarely if ever do you come back to confirm which of those changes were necessary.
Tim
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