6 layer stackup, 4mil trace

[EPC-EPDAC]

I'm looking for stack up recommendations (keeping in mind readily available materials) for a 6 layer board I'm working on.

Design requirements dictate the following:

- maximum 6 layers
- lots of high speed traces DDR3, SERDES, Gbit ETH, USB2.0 etc
- high speed signals due to BGA and space limitations need to be ~4mils wide

So for 50/100Ohm with 4mil traces, the two inner signal layers need to be close to the ground and VCC planes (about 6 mils), this results in a total stack up of only 35mils assuming 4.3mil outer cores and 8 mil center core. So either I have a "thin" PCB at 35 mils or increase the center core to 35 mils or so and that will hurt the inter-plane capacitance.

So is a less than nominal 63 mil board a bad idea (perhaps to much board flex?) or do the advantages of more inter-plane capacitance outweigh a thin board?

Any 50 Ohm, 4 mil trace, 6 layer stack up suggestions are welcome

[nctnico]

I wouldn't bother with matched impedances to memory. Usually the impedance of memory can adjusted and it isn't very cricital when traces are short (follow the PCB routing instructions). For a 6 layer board I usually have:
signal1
ground
power1 (copper pours)
signal2
power2 (copper pours)
signal3

This gives you the signal1 and signal3 layers for matched impedance traces (edit: signal2 should have been signal3).

[TommyGunn]

This is a very good write up on layer stackups. He covers most advantages and disadvantages for different stackups.

http://www.hottconsultants.com/tips.html

Here is the part on 6 layers but i would suggest reading his whole PCB stackup guide.

http://www.hottconsultants.com/techtips/pcb-stack-up-3.html