Altium article on never using ground pours

[thm_w]

https://resources.altium.com/pcb-design-blog/on-shaky-ground-the-arguments-against-copper-pours

Fail of an article or?

"The ultimate result is that there are no pluses in using copper ground pours."

Ok, clearly not the case as some were stated in the article..


"When the copper is thick, the full perimeter heat sink makes de-soldering in repair and service operations more difficult."

So lets ignore the fact that a huge percentage of electronics is not designed for repair. It is very simple to add thermal reliefs to all of your component pads, it is even enabled by default in Altium. 

[Circlotron]

I'd say a big plus is you don't have to worry about a ground connection snaking around the board and getting in the way of everything else. Just run all your signal and power tracks, then pour your ground. Makes it very easy to have super short connections to both ends of local bypass caps.

[T3sl4co1l]

Bahahaha!

It's like watching U.S. House Republicans making an argument.  The goalposts constantly move, the definitions are left up to the imagination, and the arguments are still specious or non-sequitur.

I still can't tell if they mean fill on a signal layer, or including inner layers or planes.

And it's not like you can't put thermals on the pads.  Solders fine!  Or other strategies, for example clearing other layers around a pad (so only one layer of thermals connects) then placing vias around the pad so it still connects across all layers locally.

Tim

[SiliconWizard]

This article is pretty void.

As it's on an Altium official blog, we could go as far as questioning whether this is not meant to discourage people from using copper pours because there are nasty pour bugs in AD.

[Eternauta]

Even from personal experience I have been convinced that the thesis that dividing the ground plane (AGND, DGND, IO_GND) is worse than a single ground plane is valid.
But the article does not bring any convincing argument or data against the ground plane (single or splitted).

[tszaboo]

Wow, that is one "expert" that seems to be releasing "articles" on the regular basis. The articles include:
- Dont put ferrite in the power rail. Proof, on eye diagram of a signal, with badly sized ferrite bead on a 3 GBIT/s SERDES.
- The other talks about "ultra low power design" and gets iPhone as an example.
- The third one is a two page article on how to design militarily satellites.

[SiliconWizard]

Wow, that is one "expert" that seems to be releasing "articles" on the regular basis. The articles include:
- Dont put ferrite in the power rail. Proof, on eye diagram of a signal, with badly sized ferrite bead on a 3 GBIT/s SERDES.
- The other talks about "ultra low power design" and gets iPhone as an example.
- The third one is a two page article on how to design militarily satellites.

 

[tycz]

Some engineers have a habit of filling all the empty space on a signal layer with copper and connect it to ground. The article is just pointing out that the often perceived benefits of this (reduced EMI, etc) are not valid on multilayer boards (ie. those that already have a dedicated ground plane). Then it talks about one case where ground pours are genuinely useful (increasing interplane capacitance). It seems a perfectly good article to me... is it wrong? If so, what are the real benefits of these copper islands?

The points about excess copper negatively affecting repairability is true in my experience. If a through hale capacitor is connected to multiple copper pours as well as the ground plane (even with thermals) it becomes very difficult to remove with an ordinary repair tech grade soldering iron.

[T3sl4co1l]

Not invalid, I would say not worth it.

The coupling factor between adjacent traces on a given layer, over a ground plane, is pretty modest.  On the order of 10-30%.  This is all you need to know: the shielding benefit from grounding here, is the same as the coupling between traces.  (Fine, very slightly different: because ground is typically extended, whereas an adjacent trace is narrow, the trace won't gather 100% of the field in that direction.  The difference is extremely small, because the amount of field extending beyond an adjacent trace is tiny, fractional percentage.  In other words, coupling drops off rapidly with distance between traces, especially when there's metal inbetween.)

Which is also why going with CPW allows a modest (5-20%?) reduction in trace width: the shielding manifests as reduction in characteristic impedance.

The far field (relevant to RFI) is also reduced, though again not by much, because the equivalent geometry is still a piece of metal, in or over, another piece of metal.  You've just changed the offset between the faces, which slightly changes the effective area of the trace.  Again, a reduction, just not much.

I almost never bother with signal layer fill, because stitching it is a pain -- the vias have to resolve across four layers, including routing and components -- especially when components are on both sides.

I do tend to fill heavier power supplies, but mainly for current, inductance and thermal reasons.  I also prefer polygons for those layouts, so it isn't as meaningful to call it "fill" when that's how the connections are designed in the first place.

I've filled sensitive and (noncritical) RF stuff from time to time, but I doubt it's made any difference (again, typically a dB or two).

As for 2-layer boards, I believe the complaint was... you can't have a contiguous plane anyway, so why bother?  I don't even...  Sure, you can't have perfectly contiguous ground where traces cross, but you have a minimum ground loop path of two vias and a negative trace width*, which isn't going to matter until you're pushing <200ps edges.

The EMI performance of a two-layer board with low to medium density placement, and almost everything over ground plane, stitched, is only slightly poorer than a proper 4-layer board with planes.  (You should have a fair amount of board area with overlapping pours -- where they can be stitched -- and a minimum of board area where only traces, or SMT pads and traces, are crossing, i.e., where no ground can pour on either layer.  This precludes high density, double-sided placement, but is very practical where size is not an issue.)

*That is, the negative space the trace cuts out of the pour.

Tim

[thm_w]

Some engineers have a habit of filling all the empty space on a signal layer with copper and connect it to ground. The article is just pointing out that the often perceived benefits of this (reduced EMI, etc) are not valid on multilayer boards (ie. those that already have a dedicated ground plane). Then it talks about one case where ground pours are genuinely useful (increasing interplane capacitance). It seems a perfectly good article to me... is it wrong? If so, what are the real benefits of these copper islands?

OK this is a useful recommendation. But if I have a two layer board, do I not fill one side? Not fill both?
Altium has an option to "remove islands" in pours, why wouldn't they find a way to make a point about that or perhaps and example PCB where you can actually see the board details.

The points about excess copper negatively affecting repairability is true in my experience. If a through hale capacitor is connected to multiple copper pours as well as the ground plane (even with thermals) it becomes very difficult to remove with an ordinary repair tech grade soldering iron.

You can get a decent $300 soldering iron or $200 preheater for repairs. If boards are actually being repaired in any sort of volume, this will pay for itself within a few days of work.

[PlainName]

don't have to worry about a ground connection snaking around the board and getting in the way of everything else. Just run all your signal and power tracks, then pour your ground.

That assumes a ground plane layer, doesn't it? If not, you can get to the end and find you have isolated ground pins. For 2-layer boards I always route ground as a power net before pouring to ensure the no connection is reliant on the pour.

[nctnico]

https://resources.altium.com/pcb-design-blog/on-shaky-ground-the-arguments-against-copper-pours

Fail of an article or?

"The ultimate result is that there are no pluses in using copper ground pours."

Ok, clearly not the case as some were stated in the article..


"When the copper is thick, the full perimeter heat sink makes de-soldering in repair and service operations more difficult."

So lets ignore the fact that a huge percentage of electronics is not designed for repair. It is very simple to add thermal reliefs to all of your component pads, it is even enabled by default in Altium. 

To me the article is bogus. First the article says ground pours are bad and then goes on to show ground pours are actually benificial to reduce emissions  Perhaps the problem is that Altium can't remove patch antennas. Orcad PCB designer / Allegro has an option to remove unconnected copper (patch antennas) and antenna shaped structures from copper pours.

[T3sl4co1l]

AD removes unconnected patches if you tag it to, but not peninsulas.

Tim

[DerekG]

One of the mains reasons for copper pours is that it reduces the amount of etchant that is required for production quantities. This in turn reduces the cost from the board shop. Also less copper in solution then has to be dealt with.

[SiliconWizard]

One other obvious reason for ground pours is that it's a cheap and simple way of lowering all impedance paths to ground (provided you stitch it correctly - not hard, sometimes a bit tedious). Of course for a > 2-layer PCB with a dedicated ground plane layer, this is a lot less useful, but otherwise, it can be much harder (not impossible!) to get your grounding right without a ground pour (and you'll realize it when it's too late.)

[T3sl4co1l]

I never found the etching argument persuasive.  I expect it's down in the noise at least until you're doing punched phenolic.

One could just as well argue that more copper needs more plating (time or material), or that more etching means less copper recycled from the bath, etc.

Both arguments have just as much justification; note it's all speculation until numbers are given!

One other obvious reason for ground pours is that it's a cheap and simple way of lowering all impedance paths to ground (provided you stitch it correctly - not hard, sometimes a bit tedious). Of course for a > 2-layer PCB with a dedicated ground plane layer, this is a lot less useful, but otherwise, it can be much harder (not impossible!) to get your grounding right without a ground pour (and you'll realize it when it's too late.)

Yes, this is another perspective on ground-as-shield.  Better isolation between traces, lower (and controllable) trace impedance.  Having a low impedance between ground points is effectively self-shielding, i.e., the self inductance is reduced.

Regarding impedance -- the impedance of a random trace through space is probably in the 150-300 ohm range.  On a board with routed ground(s), this is as likely to be the impedance to ground as to neighboring traces -- strong coupling, through myriad coupling paths -- an intractable matrix.  Even with EMI shields around such a board (example: classic computers like the ZX81), it'll be towards the low side (15-200 ohms?), and without EMI springs making frequent contact to the shield (usually only contacting around the board edge, where it's clamped on), there's still a long trace length from that shield back to the trace.

Whereas with ground, a 2-layer board can reasonably have 100-150 ohm traces, comfortable for CMOS, and TTL with modest fanout.  Also a good match for ribbon cable (alternate signal and ground assignments).  Low impedances aren't so reasonable, with trace widths comparable to half the board thickness, give or take.

Tim

[exmadscientist]

I actually mostly agree with the article, but I think it does a poor job of being clear about what it's arguing for.

First off, it's explicitly about multilayer boards. Good 2-layer board design is an art and follows its own rules. (Aside: I've had engineers tell me it's never worth it to go for a 2-layer board these days, given the current price of 4-layers. This ignores the fact that while, sure, a 4-layer nowadays is readily affordable and probably around the cost of a 2-layer in years past, have you looked at how cheap 2-layer actually is? On a relative scale 4-layer is still a huge cost hit... but that's only because on an absolute scale, 2-layer boards are basically free. At modest volumes, that's a great benefit to have and frees up some pennies to be put to work elsewhere in the product.)

Let's take a look at an 8-layer design that I did a while back, and its stackup in terms of power, ground, and signal layers:

• Signal / component pads
• Ground
• Power
• Power
• Power
• Signal
• Ground
• Signal / component pads

Additionally I used a "fat core" design where the L1-L2, L2-L3, and L3-L4 spacings were all close (~5mil) and the L4-L5 spacing was large (the balance of the board thickness). As usual it was symmetric so L1-L2 matched L7-L8, etc. (Also also, this is all from memory so I might have some details wrong.)

The first thing you note about this design is it's got a lot of power planes. I wasn't responsible for the schematic on this one, but did do the layout. Figuring out how to route all of the rails was an issue and required a few split planes. Fortunately there were enough planes available that I could dedicate full planes to the more important rails and the split planes for the less important (fewer connections, lower frequency, sometimes higher current point-to-point-ish routing). I think the best thing that could be done to improve this design from an EMC point of view would have been to reduce the number of power rails (it had several power muxes) to simplify power flow.

Now we've reached the point that we can talk about the article: the question is, what do you do with the unused space on L1, L6, and L8?

L6 is easy: everything I've ever read says you really want to match the copper balance here with L3. L3 is a plane layer and will be 90+% filled with copper. L6 is a lightly used signal layer with natural copper fill level maybe 5% or 10%. To avoid warping in the press and uneven resin flow, we'd like L6 to match L3. Thus, L6 should get a ground or power fill. To avoid radiation, we need to tie it down to something (not float it); since this design already has multiple ground layers, there are ground stitching vias everywhere, and so connecting to ground is simple. Since we are not relying on this layer for any aspect of our electrical performance, we can be fairly liberal with it, choosing fat plane traces and pullbacks. We also don't need to match L3 exactly in copper fill; we only need to push it from say 5% to 80%. So if there are a few open spaces, that's fine. About the only thing we need to be careful of is avoiding islands and peninsulas as they can radiate.

What to do about L1 and L8 is, I think, the point that the article is trying to make, and I think most people here are in agreement that filling them with ground is just not very useful. Sure, if it's done well, it won't hurt much either, but that's a lot more work than leaving the layers open for no real benefit. There's a ground plane 5 mils down; having another ground fill 5 mils to the side, on a layer that's already tightly packed with components and traces, really doesn't do much.

[nctnico]

Well, there is one good reason to have ground and power pours on the top and bottom layer in multilayer designs: you'll also be parallelling vias from decoupling capacitors to the power planes and thus lowering the impedance of the power distribution network. Having power planes is nice but the self inductance of the vias is quite high.