Analog and Digital Ground Connection Question

[failsafe]

Hello All,

First post, so I wanted to say thanks to Dave for all of the great content.  I have watched every EEVblog video and listened to almost all of the amp hour podcasts.  Great stuff, thanks.

Well onto my question.  I have created a PCB that includes both Analog and Digital circuitry.  It includes a DC-DC converter, micro, 3 asics (quadrature decoders), an rs485 transceiver, 3 AD7685 ADCs, and 4 instrumentation amplifiers.

I have implemented a 30 mil isolation border between the analog and digital grounds.  The PCB stackup is: (Top Layer - Signal/Ground, Second Layer - Power[+5.25V,-5.25V, 3.3V], Third Layer - Signals, Bottom Layer - Ground).  The isolation border exists on the top layer and the bottom layer.

Currently, I have joined the analog and digital grounds at one point near the common ground connection of the DC-DC converter.  I am not sure if this is the right technique though.  I was hoping to get everyone else's opinion on where they would connect the analog ground to the digital ground.

A couple of notes:

1)  I have googled this and have found multiple different opinions on where to connect the ground planes.  The datasheet for AD7685 and this article http://www.hottconsultants.com/techtips/split-gnd-plane.html by Henry Ott suggest connecting the grounds underneath the ADCS.  Then again, this article http://www.msc-ge.com/download/lattice/files/an6012.pdf by Lattice suggest placing the ground connection near the common ground at the voltage regulator.

2)  I have attached a simplified picture of the pcb, highlighting the important areas. 

Please feel free to comment.
Thanks

[jahonen]

I'd use completely contiguous ground plane (as you have a multilayer board) and just group components correctly, like in H. Ott's paper. That will result lowest voltage difference between ADC DGND and AGND pins, as they are shorted with as low impedance connection as possible. At high frequencies, and for RF-immunity, that is often the simplest and best solution. Especially considering that you have multiple points which want to be the connection point.

Regards,
Janne

[failsafe]

Thank you greatly for the reply.  I am THE EE at work and surrounded by nothing but MEs (no offense MEs atleast you are not Civils ha!).  Therefore I do a little bit of everything.  It makes it hard to be a master at anything in particular though.  Also, quick edit:  I am using 3 AD7685 ADCs not AD7865 ADCs.  I have corrected the original post; Just a bit of dyslexia kicking in. 

As far as the DGND and AGND the AD7685 chip is a bit peculiar.  It does not have a DGND and an AGND pin.  It only has the one GND and that is connected to the analog ground of my circuit.  I am guessing digital ground and analog ground are connected internally in the package.  Here is the link: http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad7685/products/product.html.  Knowing this now, does your advice still stand?

It does though have 2 different VCCs.  The 5.25V VDD connection is on the analog ground side of my circuit.  The 3.3V VCC (IO) connection is on the digital ground side of the pcb.  It is worth noting though that I have placed a .1uF decoupling cap on the 3.3V VCC connection, but that decoupling cap's ground connection is attached to the digital ground.


Personally, I am leaning towards Henry Ott's suggestion for the Higher resolution ADC circuit.  This is due to ADC#1 measuring a highly amplified load cell signal.  I have attached the image that I am referring to.

Does anyone else have an opinion?  Thanks for the support guys.

[jahonen]

Yes, I would still make ground contiguous, it is usually simpler and has better EMC-properties. Thus it makes your chance of succeeding greater   Datasheet says that

At least one ground plane should be used. It could be common or split between the digital and analog section. In the latter case, the planes should be joined underneath the AD7685.

Like I said, because you have multiple ADC's, it might be simplest not to use any splits. My experience has been that there are other coupling paths at high frequencies which have stronger effect than just IR drop across the ground plane.

Regards,
Janne

[Neilm]

I completely agree with Janne - you have a multilayer board, just use one 0V.

A few years ago I had to rework several products as the EMC standard they had to meet had just changed. Most of these products were quite old and only used 2 layer boards and had separate 0V in them. Some of these had known issues in certain environments.

My solution for these was to make them 4 layer PCBs with a common 0V. In almost all cases, this simple change made the unit pass. A couple of units had their issues sorted at the same time as the good 0V reference become much less sensitive to noise. We were even able to tighten the spec of a couple. The couple of units that did not pass performed much better than they had prior to the change - just not enough to pass the new standards requirements.

Neil

[failsafe]

Fantastic Feedback, thank you both.

There really is no replacement for experience.
I will change my design to use a full ground pour on both the Top and Bottom layers. 

I was very concerned with noise getting into my ADC#1 circuit.  The signals that it measures vary from approx 10uV to a maximum of only 7 mV. Therefore a very large gain was necessary to span my 0-5V ADC range.  The other 2 ADC circuits are trivial.
I already created a prototype pcb circuit using a split ground plane setup and it works well but not perfect.  I am happy I decided to ask here before moving forward.  Thank you for reaching across the pond to help a fellow engineer out.

One last thing: While investigating this issue, I noticed something I have been doing lately regarding bypass capacitors.  I was going to make a new topic but maybe I'll just ask here since it does pertain to the ADCs in question.

I have gotten into the habit of placing the via that connects a VCC pin to its respective power plane between the pin and the bypass capacitor.  I created a image to demonstrate.  It seems I have gotten into the habit of using Version#1 layout.  (Red circle = Via to power plane.  Blue Square= 0508 bypass capacitor).
Does it make any difference if I use the Version#1 scheme instead of Version#2 scheme?  Should I switch all of my connections to the Version#2 scheme?   

Thinking about current flow, I seem to think Version#2 is the better way to go.  Sometimes though actual board layout favors Version#1.  I wonder how much it matters.

Thanks again.  I am truly appreciative.
-Karl

[jahonen]

I personally prefer your #2 style, that's what I generally use. If you can, it might be wise to use that instead of #1.

Regards,
Janne

[ejeffrey]

I would prefer #2.  High frequency supply current fluctuations (i.e., the surge when a digital output switches low to high and charges up a few pF of capacitance) flow through the bypass capacitor not the power supply trace.  The bulk capacitors on the board are too far away to help and have too much inductance.  The power plane has distributed capacitance with extremely low inductance, but it just doesn't have enough capacity.   Therefore you need to rely on the bypass cap, and you want it to have as low a inductance as practical.

[failsafe]

I was looking through my old posts and remembered this circuit. I just wanted to update it in case anyone finds it in a google search.

The final version of that board did not look much like the picture I posted. Looking back now it is obvious to me that the ground plane connection between the analog and digital sides of the board would have created issues.

I produced multiple versions of that board. I tried different strategies regarding analog, digital ground isolation. The design I eventually went with was just a solid ground plane. I was able to decrease the noise in the ADCs by moving the digital circuits further away and not worrying about splitting ground planes. Ground plane strategies still interest me though. I will still try split planes in the future, but won't worry about using solid ground planes as much.

As far as the via layout. I tried both strategies. I didn't really notice any differences in performance. I usually do a pretty good job of keeping connections as tight as possible, so that might explain the lack of performance difference.

Anyway, just thought I would update for completeness.
Thanks,
Karl