I'm reading Yan Tan's dissertation "Algorithmic studies in PCB design"
https://www.ideals.illinois.edu/bitstream/handle/2142/18367/Yan_Tan.pdf?sequence=1&isAllowed=y. He presents a series of algorithms for escaping traces from BGA pins, keeping differential pairs routed together, ordering escaped traces to that they can be routed to their destination on a plane (i.e. without crossing), and assigning traces to a minimum number of signal layers. He seems to have been employed by Synopsys Inc during or around this time.
The algorithms that I've understood so far seem quite compelling. However, they are clearly "computer science" solutions to "electrical engineering" problems. An algorithm might provably be able to (say) escape pins using the least amount of copper trace and obeying the maximum number of orthogonal/diagonal connections across an inter-pin tile, ut these results are not (afaik) transported into the physical domain. There are no SPICE simulations, no designs being fabricated, no oscilloscopes measuring signal integrity, etc.
So I'd like to understand: How do these kind of algorithms relate to industrial practice? If I write a program to implement these algorithms can I expect the resulting boards to actually work? Are these kind of algorithms commonly used in EDA tools and if so which tiers (e.g. Eagle, Altium, Cadence, etc)? Supposing you had access to software that does this, would you actually use it e.g. for escaping large numbers of I/O pins from large FPGAs?