Via and ground plane question

[hozone]

Hello,

I'm an amateur PCB designer.
I usually design 2 layer PCB.
Almost always I build boards with two plane, one ground and one power.
Sometimes I use VIAs to connect GND and PWR, but most of the time ground and power lines are directly routed to the pins that needs GND and VCC.
I'm lately watching pro PCBs, I've found that GND and PWR vias are heavy used, expecially GND.
I'm wondering if a better design would be to use GND and PWR VIAs "ALMOST ALWAYS".

Thanks for any of your tips!

[Doctorandus_P]

A good ground plane is a very important part of a PCB. One of the guys at altium has made a 2 hour (and some minutes) video about it, and if you're into improving your PCB design skills it really is worth watching.

For a two layer PCB, usually all smt stuff is on the top, and this means the GND plane has to be on the bottom to be able to keep it continuous. As a result everything is connected with via's to the GND plane.

Normally a lot of decoupling capacitors are spread around the PCB. The result of this is that the power supply only has to deliver a DC current and the AC ripple current at higher frequencies is quite low. This also means that the power supply just has to be able to deliver this current. Fairly wide tracks to lower the resistance are usually used, but the power supply itself does not really need a plane.

But this is just a few rules of thumb and a gross simplification. That 2 hour video from altium is from a man with a grey beard who knows his stuff. Robert Feranec also has quite a lot of videos about PCB design

[bpiphany]

Here's a Feranec video about power planes or no.



I've had many of my hobbyist PCB layout presumptions challenged by watching his videos.

[hozone]

Thanks all!

I've watch that video. Power plane I would like to use is not for high current reason, it's to avoid power route, to give more "space" for signal routes.

This video clarify half of my doubts:


It seems, in a few:
* one via per GND, on ground plane
* one via per PWR pin, on power plane

BUT, on the video bpiphany suggested, seems power plane are "evil".

So now I've a doubt, to power plane or not?

I'm speaking of 2 layer boards.

[Feynman]

While a solid ground plane should be beneficial in most designs, a power plane is often times optional (but certainly not "evil" per se).

In designs that are rather simple (4 or 6 layers) I almost never use power planes: When possible, I make half the layers solid GND planes. And power is routed and/or poured on the signal layers.

[redkitedesign]

Normally a lot of decoupling capacitors are spread around the PCB. The result of this is that the power supply only has to deliver a DC current and the AC ripple current at higher frequencies is quite low. This also means that the power supply just has to be able to deliver this current. Fairly wide tracks to lower the resistance are usually used, but the power supply itself does not really need a plane.

Nope. The current in the ground net is (by definition, Kirchhoffs Current Law) the same as in the power net. Or, a different view but the same result: Every electron that goes into the power supply (at the positive terminal!) has to come out at the negative terminal (ground). Conservation of Mass is a nice law there.

However, since pretty much all functionality of your design is defined in voltages with respect to ground, it makes everything a lot easier if at least the ground is stable and the same throughout the design. Hence the ground plane before the power plane.

But as soon as you've got more than 2 layers, consider adding a power plane. For 4-layers, I often use the middle layers for power and ground, and the outer layers for signals. That allows me to route a lot of signals (all between nearby SMD component pins) without via's. Power and ground pins get (preferably) routed to a decoupling cap, and then on to a via.

Additionally, this setup allows me to access all traces in the prototype fase, giving me maximal design modification freedom.

[bpiphany]

I think the main take-away from the video I linked is that you should likely consider extra ground planes rather than adding power planes.  Example:

In a 4-layer stack-up if you have signal-gnd-power-signal layers, the traces on the gnd side will have their return path directly underneath in the gnd layer, but the traces on the power side won't.

A signal/power-gnd-gnd-signal/power stack-up doesn't suffer from that same problem. (And you still have options to solve the trickiest parts of the routing by cheating it on the gnd layers.)

With more than 4-layers, and exotic via configurations, there are of course many more options to stack-ups. Having power planes is very convenient for routing, not as much for EMC-issues.

[Doctorandus_P]

Nope. The current in the ground net is (by definition, Kirchhoffs Current Law) the same as in the power net. Or, a different view but the same result: Every electron that goes into the power supply (at the positive terminal!) has to come out at the negative terminal (ground). Conservation of Mass is a nice law there.

No it's not.  Kirchhoff deals with a single loop at a time, not with a whole net.
The decoupling capacitors filter out most of the high frequency content of the current from the power delivery system (i.e. cables to the PCB)

Conservation of mass? Electrons don't have much mass. I guess it even depends on their speed too (although drift speed due to current is low).

The GND plane is also the reference for all signal tracks.
Above a few kHz the main impedance of any track is the loop inductance, and not the DC resistance, and above those frequencies minimizing the loop inductance is the main goal, and that is done by putting a GND track directly below each signal track.
And to avoid getting mad, this is simplified in practice to a full GND plane. A 4 layer PCB (with internal GND layer(s)) has the additional advantage that the GND plane is much closer to the tracks. It goes from approx 1.5mm (the PCB thickness) to 0.1mm or so. so a factor of 10 reduction in the loop inductance.

As long as the local decoupling (and buffer caps) is good enough to keep the frequency content of power delivered to the PCB well below a kHz, then the main concern for the power net is the DC resistance. All the higher AC currents exist then only between the decoupling caps and the IC's (and this distance must be minimized).

I've also done a simple search. The man with the grey beard appears to have a name. (It's Rick Hartley).
The youtube video I mentioned earlier is:

[LIVE] How to Achieve Proper Grounding - Rick Hartley - Expert Live Training (US)

[hozone]

Thanks all.

Speaking about a simpler 2 layer boards (1.6mm as example), can I summarize like so?

• Put a GND plane and use vias to connect all the GND to that plane. Try not to cut the plane.
• Prefer power trace as route, but a power line is not so bad, expecially if we are not talking about high freq.

Going into pratical, the board I'm designing is a mixed signal, decoupled, low freq one.
It has 24V in, this voltage is then converted to:

• +- 12V decoupled (DC-DC conterted + LTO) and 5V ref, for a +-10V voltage output and DAC (the 5V ref)
• 24V decoupled from the main 24V (DC-DC conterted), for a 4..20mA current output
• 3.3V decoupled (DC-DC conterted + LTO), for the MCU - STM32
• Main 24V, for digital output (decoupled from the MCU by optocouplers)

So I have 3 different GND, each one with a power line

• +-12V and 24V share the same GND, for analog output
• 3.3V GND, for MCU
• main GND, for digital output

I'm thinking about a splitted power plane on bottom, on the top the relative power plane distribution.
What's your suggestions?

Note: at present the board as GND plane on bottom and top, but is a "poured" one. It works, but I want something better. I can not share the design of this board unluckily.

[eb4fbz]

2 Layer boards are the real evil. 4 Layer are not much better if 1.6mm, not so bad if 0.8mm thick. For mixed signal boards with more than 1 power net I would suggest you to change to 6 layers.

[redkitedesign]

In a 4-layer stack-up if you have signal-gnd-power-signal layers, the traces on the gnd side will have their return path directly underneath in the gnd layer, but the traces on the power side won't.

I don't buy it. The gnd plane may be 0.3mm further away for the top layer signals, but its still there. That 0.3mm difference wont matter compared to a larger loop around a component in your power distribution because you don't have a power plane.

Nope. The current in the ground net is (by definition, Kirchhoffs Current Law) the same as in the power net. Or, a different view but the same result: Every electron that goes into the power supply (at the positive terminal!) has to come out at the negative terminal (ground). Conservation of Mass is a nice law there.

No it's not.  Kirchhoff deals with a single loop at a time, not with a whole net.
The decoupling capacitors filter out most of the high frequency content of the current from the power delivery system (i.e. cables to the PCB)

Kirchhoff still applies. Every net is a combination of an finite number of loops.  Decoupling caps make smaller loops for AC current, but any current from the gnd plane into the cap also flows in the power net at the other side of the cap. Thats how caps work, the current at both sides is always the same.

If you can safely reduce your power net to a simple trace by careful use of caps, you can also reduce your ground net to a trace.

Conservation of mass? Electrons don't have much mass. I guess it even depends on their speed too (although drift speed due to current is low).

they have (rest-)mass. Thus conservation of mass applies.
Same for charge, if a power supply would deliver more electrons to the load than the load returns (which is what happens if there is more current in the ground plane then in the power trace) the power supply would get charged. That doesn't happen.

The GND plane is also the reference for all signal tracks.
Above a few kHz the main impedance of any track is the loop inductance, and not the DC resistance, and above those frequencies minimizing the loop inductance is the main goal, and that is done by putting a GND track directly below each signal track.
And to avoid getting mad, this is simplified in practice to a full GND plane. A 4 layer PCB (with internal GND layer(s)) has the additional advantage that the GND plane is much closer to the tracks. It goes from approx 1.5mm (the PCB thickness) to 0.1mm or so. so a factor of 10 reduction in the loop inductance.

Every signal is driven by a push-pull pair. Whenever that signal is positive, the current comes from the positive power supply. Thus the loop is not through ground, bu through power.
Decoupling capacitors help to redirect the AC part of that current through ground, but in effectively you are putting a cap in series with your signal.

Proper power planes prevent that series cap.

[bpiphany]

...

I suggest you watch the videos and come back after.

[hozone]

Thanks all.
I found that this topic is not as simple as I belive some days ago when I ask my first question.
I'm watching a lot of videos, my sources at present are:
+ Altium academy
+ Robert Feranec
+ Phil’s Lab

I think Robert channel is the most exaustive, but even not simpler to understaind, it takes time and studies... but it's thing I've to work on.

Now I have more questions in mind.
Copper pour or not?
Split plane?
Gnd plane?

Up to now it seems to me this 4 layer stack is the most used
SIG/PWR
GND
GND
SIG/PWR
With a single GND.
But I have more than one GND, so I've to investigate further.

2 Layer boards are the real evil. 4 Layer are not much better if 1.6mm, not so bad if 0.8mm thick. For mixed signal boards with more than 1 power net I would suggest you to change to 6 layers.

What stack do you suggest?