Confused about creating SMD capacitor footprint libraries.

[pigrew]

How should I decide on which footprint for chip capacitors to use? Should I create a separate footprint for caps from each manufacturer (and each of their dimensional tolerances)?

I have so little experience with commercial board assembly that I see a multitude of answers, which I've tried to outline below.

(I'm having some expensive boards assembled (down to 0201 and 0.4mm PQFN pitches...., with "HDI" technology). I don't want them to be screwed up. I'm also trying to navigate using separate PCB fab and assembly companies.)

Do people normally use a footprint generator to calculate the pad sizes, or go by the manufacturer recommended footprints? Or should I ask the assembly company to tell me what pad sizes to use?

Or do people not normally worry about it, as they swap between brands of passives quite often, so there is no point designing for a particular model? Though, there are some like with epoxy terminals which are much more variable than the run-of-the-mill parts.

Using Murata 0402, 0.5mm height, using "nominal" dimensions as an example, I see that there are three separate tolerances for the lengths of the capacitor (1.0 +/- 0.05), (1.0 +/- 0.1) and (1.0+/-0.2). Plugging them into the "Library Expert Pro" utility, these generate three different footprint geometries. Which should I use? It seems I need to lookup each capacitor individually, and associate them manually? Or just use an average value for all 0402 size? Or use the loosest tolerance to insure that there is enough clearance between parts for assembly?

I mostly use Murata capacitors. I can download a table of their capacitors from their product search (with size tolerances), but only 1000 at a time. Is there a better way to bulk download the part numbers more than 1000 at a time, to import them into a component library (for Altium, sqlite database built from Python scripts)?

[PlainName]

The specific pad dimensions would surely depend a lot on what you're using to stick the legs to them - the particular solder makeup, temperature profile, etc - and the part manufacturer won't know any of that. They will provide their own take on it, of course, but if you use more than one manufacturer's parts on a board, whose recommended process do you follow? I think it's safe to say that the manufacturers recommendations are known to work, but that doesn't mean that something else won't.

And, if you think about it, given the exact same chip package, should two identical parts from different manufacturers work with the same single process, even if their recommendations are slightly different?

Hmmm. I get the feeling I am sticking my head above the parapet here given that no-one else has attempted a reply

[nctnico]

I just use the libraries which came with the PCB package. These are generic footprints and so far have worked well at various assemblers.

[pigrew]

And, if you think about it, given the exact same chip package, should two identical parts from different manufacturers work with the same single process, even if their recommendations are slightly different?

The trouble is that the packages  (length, width, height, termination width, and tolerances thereof) are different between manufacturers, and even within a manufacturer's product's. Sometimes, for example with GRM155* capacitors, different values have different dimensional tolerances within one series). I've found that the termination width is often different between manufacturers. I feel like there is minimal standardization, but everyone typically considers them all the same and uses a generic footprint?

Another issue with tolerances is that while the pads may solder down fine, but the parts are laid out too close together if one goes from a manufacturer with tight tolerances to one with loose tolerances. (I keep ending up working on very space-constrained designs, so want to pack everything as tightly as possible).

On the other hand, I'm probably making much ado about nothing, and I just need to be told that I don't need to be so precise, and boards usually work out fine. The boards I'm working on currently are pretty expensive, so I don't want to screw them up.

[T3sl4co1l]

IPC calculated footprints are generally the place to be.  The dimensions are most likely to suit all components compliant with the body dimensions, and more likely that CMs have tuned their process to those dimensions.

Regarding termination width: it's bullshit, and I suspect some don't even read the dimensions they put there, or derive the dimensions from their actual process.  I think I've seen (but don't have an example handy unfortunately, so this is just hearsay) dimensions and tolerances that suggest the device can sometimes be shorted out from the factory (metallizations overlapping).  But of course, a real part would never be /that/ bad.

Most of all, sanity-check the dimensions you're using, and review the footprint yourself.  Preferably run an automated DFM check.  Preferably purchase real parts ahead of time, and measure them yourself.  Plan a small alpha build where you expect some things to go wrong, and fix "all" of them in the beta build.  Etc.

Tim

[warpco]

Thanks god someone asked about it! This question has been bothering me for a couple of weeks. In fact, it is much wider than just about SMD capacitors. I could ask the same thing about all components: passives, discretes, ICs, through-hole, surface-mount.

At first it seems that using IPC calculator together with dimensions provided by a manufacturer is the best option. You can't go wrong with it. Yeah, sometimes datasheets lie, but it is the most reliable source of information anyway. It also allows you to create accurate 3D models for your components. On the other hand, the mere thought of having to create (almost) identical footprints/3D models over and over again makes me crazy! I doubt that all these hair-thin differences make any sense, and you definitely don't need this accurate 3D models.

I think the answer to this question comes only with experience... Unfortunately I don't have such experience. 

[T3sl4co1l]

The true answer is it's a feedback process, from assembly to design.  There is plenty of room to, say, adjust the toe fillet for a soldering iron versus wave versus reflow process, or the width of a pad for how much side fillet (if any) a real component has, or the pad gap / heel fillet if you're having positioning or tombstoning problems.

So as you can see it's mostly a production issue.

If you're doing one-offs, occasional difficulty in assembly is just a given.

Follow datasheets and standards as well as you can, and allow an extra week or two for ordering replacement parts that you thought you put in correctly, but actually ended up the wrong size anyway.

Have wirewrap wire and glue on hand to rewire bad pinouts.   Preferably with UV-cure soldermask to gloop over the joints, so they aren't just flapping in the breeze.

Have a fine tipped soldering iron and hot air machine so you can do most SMT rework.  Or do it through a CM who does all this automatically.  Can be expensive, yes, but it's a big time saver for you!

Tim

[pigrew]

I'm doing very expensive runs of limited quantities (HDI rigid flex), so I don't want to get it wrong the first time. TLDR: capacitor dimensional tolerances mattered for the PCB I'm working on.

I'm limited to a particular form-factor and the placement of certain passives. (Probably shouldn't say more than publicly that due to NDA.) I need to substitute a capacitor (which was designed ONLY for conductive glue mounting) with one that is reflow-approved, and my replacement's tolerances were too large (+/- 0.3 vs +/- 0.1 mm) that the capacitors bumped into each-other on the board... Perhaps in reality it would have worked, but I'm not sure and I don't want to risk the component batch the assembler uses for a second assembly run being different than the one that I'd order now... (I wanted flexible termination, but these all have looser tolerances).

Thanks god someone asked about it! This question has been bothering me for a couple of weeks. In fact, it is much wider than just about SMD capacitors. I could ask the same thing about all components: passives, discretes, ICs, through-hole, surface-mount.

Yes, but capacitors are the thing that will likely cause issues. Designers (mostly) know that different companies have different QFN or BGA packages, so will look at their footprints per SOP. We use thousands of capacitors and normally assume they are generic, and that (0805, height=0.5 mm) should be enough to specify the footprint/3D model, but it isn't.

[olkipukki]

How should I decide on which footprint for chip capacitors to use? Should I create a separate footprint for caps from each manufacturer (and each of their dimensional tolerances)?

I have created generic High-, Medium- and Low- footprints based on IPC recommendation.
The next step, verified that Murata caps fit into these footprints. The assembly has confirmed no issues regardless how close each other placed.

Unfortunatelly, Murata passive become much more expensive and switched to alternatives, but the process was same as above.
If I found that something cannot fit into a generic footprint, that's ring an alarm. The last option be depended from one manufacturer.

[Feynman]

+1 for an IPC calculator.

I don't care too much about different tolerances. Just decide for one tolerance and stick with that (e.g. the "worst"). Since tolerances aren't part of the IPC compliant footprint name, you don't have the headache of renaming footprints with same dimensions but different tolerances.

For anything beyond that you have to talk too your assembler anyway.

But an IPC compliant footprint with one set of tolerances is the best starting point you can get.

[SiliconWizard]

The true answer is it's a feedback process, from assembly to design. 

Yup, yup, yup!

Don't hesitate to submit your PCB design to your assembler BEFORE having your PCB manufactured. Always a good idea, and the bonus is that the assembler will be ready to start with your boards much earlier this way than if you wait for the PCBs to be manufactured first.