I'm building a board with multiple ASIC's in series. Each ASIC has a footprint similar to a DFN, where there are a few IO pins on either side of the ASIC. In addition there are two large pads that supply power (V+) and ground (V-) for the high-current domain. Further, these ASIC's are connected in series, such that V- for one chip is connected to V+ for the next. The specs for this chip say that it can draw up to 45A.
The V+ and V- pads on this chip are 325 mils wide (150 mils tall). In order to carry this much current from one chip to another, I'm using 4 layers of 2oz/sqft copper, with an array of vias directly in the pads. Using PCB trace width calculators, I'm estimating that if I stretch a 325 mil wide trace/pour between the pads in all four layers, then the 2 inner layers should be able to carry approximately 9A each, while the external layers could carry approximately 18A each, for a total current capacity of 54A, assuming a maximum desired temperature change of 10 degrees C.
However, I'm trying to stick to a 4 layer board. The design I described above means that I do not have ground planes adjacent to these traces.
- Is that bad or very bad?
- What are my alternatives?
- Must I add more layers, and if so, what stack up would you recommend?
- Knowing that the pad itself is 325 mils wide, would it be possible to have a 325 mil trace on the top layer and a much wider trace on the bottom layer to carry the current? For example, if I had a 325 mil trace on top (carries 18A) and a 600 mil trace on bottom (carries 28A), is that a better alternative? I'm concerned that the vias that get the current down to the bottom layer are still confined to a 325 mil space, so I would still end up with too much heating.
Any advice you can give is appreciated. What would your thought process be in beginning layout for such a design? What considerations have I missed?