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Dealing with high current traces with few layers

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mattmunee:
I'm building a board with multiple ASIC's in series.  Each ASIC has a footprint similar to a DFN, where there are a few IO pins on either side of the ASIC.  In addition there are two large pads that supply power (V+) and ground (V-) for the high-current domain.  Further, these ASIC's are connected in series, such that V- for one chip is connected to V+ for the next.  The specs for this chip say that it can draw up to 45A. 

The V+ and V- pads on this chip are 325 mils wide (150 mils tall).  In order to carry this much current from one chip to another, I'm using 4 layers of 2oz/sqft copper, with an array of vias directly in the pads.  Using PCB trace width calculators, I'm estimating that if I stretch a 325 mil wide trace/pour between the pads in all four layers, then the 2 inner layers should be able to carry approximately 9A each, while the external layers could carry approximately 18A each, for a total current capacity of 54A, assuming a maximum desired temperature change of 10 degrees C.

However, I'm trying to stick to a 4 layer board.  The design I described above means that I do not have ground planes adjacent to these traces. 


* Is that bad or very bad? 
* What are my alternatives? 
* Must I add more layers, and if so, what stack up would you recommend?
* Knowing that the pad itself is 325 mils wide, would it be possible to have a 325 mil trace on the top layer and a much wider trace on the bottom layer to carry the current?  For example, if I had a 325 mil trace on top (carries 18A) and a 600 mil trace on bottom (carries 28A), is that a better alternative?  I'm concerned that the vias that get the current down to the bottom layer are still confined to a 325 mil space, so I would still end up with too much heating.
Any advice you can give is appreciated.  What would your thought process be in beginning layout for such a design?  What considerations have I missed?

thm_w:
Did you check the vias what sort of current they can carry?

Maybe some screenshots would help to visualize. As well as some sort of idea how fast this ASIC is switching. Do they have a datasheet or any instructions for decoupling it?

mattmunee:

--- Quote from: thm_w on May 15, 2023, 08:52:56 pm ---Did you check the vias what sort of current they can carry?

Maybe some screenshots would help to visualize. As well as some sort of idea how fast this ASIC is switching. Do they have a datasheet or any instructions for decoupling it?

--- End quote ---

Without showing too much of the design, here's a screenshot of a middle layer to show the high current trace and the vias in pad.  The via arrangement should be sufficient to get current down through the different layers, at least from a pure current-carrying-capacity perspective.  I believe the PLL of the ASIC is on the order of 1MHz, but I'm not sure how that affects the design.

ahbushnell:
Why not make the traces wider? 

mattmunee:

--- Quote from: ahbushnell on May 16, 2023, 03:33:04 pm ---Why not make the traces wider?

--- End quote ---

As I mentioned in the original post,


--- Quote ---Knowing that the pad itself is 325 mils wide, would it be possible to have a 325 mil trace on the top layer and a much wider trace on the bottom layer to carry the current?  For example, if I had a 325 mil trace on top (carries 18A) and a 600 mil trace on bottom (carries 28A), is that a better alternative?  I'm concerned that the vias that get the current down to the bottom layer are still confined to a 325 mil space, so I would still end up with too much heating.
--- End quote ---

Can I do that without excessive heating, knowing that the pad and hence the connection to a wider trace is only 325 mils?

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