Author Topic: Differential trace impedance without reference plane  (Read 2234 times)

0 Members and 1 Guest are viewing this topic.

Offline muruganmayil

  • Newbie
  • Posts: 1
  • Country: in
Differential trace impedance without reference plane
« on: February 05, 2018, 03:56:22 pm »
Hi There,
We are designing a pass through PCB by routing the isolated RJ45 signals. Please refer the below image for reference.
•   •       How to achieve differential trace impedance for isolated RJ45 signals in PCB? Even if it is 4layer since there should not be any ground/power plane under the differential pairs after magnetics.
•   •       Can we give shield ground of RJ45 connector as reference plane for these differential traces to achieve 100ohm impedance for differential traces on the PCB? If so how can we achieve the 2KV isolation between differential pair and shield ground ?
•   •       How can we achieve the differential impedance without reference plane and by using only trace width, separation and dielectric permittivity? Without using dielectric height (H) since no plane here.


Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 14735
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: Differential trace impedance without reference plane
« Reply #1 on: February 06, 2018, 05:14:57 am »
I've tried looking for that before, seems to be scant information.

This has curves which may be useful.  Doesn't look like the impedance goes low enough, which is a concern.  A lower ratio may get there.

The limiting case for trace width --> infty is a slot line,
defined only by the gap between traces and the dielectric.  (Obviously, for Ethernet which must use a TEM mode, the traces can't be infinitely wide, or returned to ground as in a slotted waveguide (finline); just assume that the impedance approaches this value for w >> h.)

This may require inconveniently wide traces.

The other option is parallel plate transmission line, which I can't find a damn thing on.  The construction is simply placing the traces in the same locations, opposite layers.  The problem is, every EE course uses this as an introduction to transmission lines, which yields only the very-wide limiting result.  No one seems to explore the case with fringing fields.

If nothing else, you can construct the geometry and simulate it with something like ATLC2.

On a practical note, if the application is only 10/100Mb, that can literally run over coathangers.  It's very tolerant to mismatch, and running traces that are good-enough will more than suffice, particularly if they are short.  Traces of only a few cm or less will probably be fine at Gb too.

Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
The following users thanked this post: mars01

Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo