Filling with GND and VDD sounds good at first, but the problem is you have slots and gaps between regions of those conductors.
You can very easily route at DC this way, and that's fine. But, real, interesting circuits are not just DC.
The problem arises when you have AC currents drawn between those gaps and regions. They act like inductors and capacitors, and you get all sorts of radio frequency noise inside the circuit, and outside it too (emissions). And susceptible the other way, like, such a circuit might be particularly vulnerable to ESD because you don't know which path the ESD current will be shunted through. It may just find a sneak path through a chip!
So the better way overall, is to pour one net on both sides, and solve the gaps by stitching with vias. Typically, vias are placed near crossing traces, on peninsulas and islands, and periodically along boundaries. If you aren't doing precision or RF work, the spacing doesn't need to be very close -- an inch or two will suffice. Concentrate on features more than general density.
Try to have ground poured on at least one side, over as much of the board area as possible. Anywhere traces overlap or cross, there's a hole in both pours. Obviously, don't run traces in parallel on both layers, at least for very much distance. Prefer to group long runs into buses on one layer.
Vias are cheap, don't be afraid to use them!
If you are doing precision RF work, you'll often employ via fences around relevant traces. The spacing is driven by the amount of error at a given frequency, so of course, if the error must be smaller, or the frequency goes higher, the spacing goes down.
For the generalization, figure on about half the layers, in a multilayer board, being dedicated to supplies connected with large pours.
Typical 4-layer stackup, the middle two are GND and VDD.
On 2-layer, you effectively create one average layer of GND by stitching pieces of both layers together, and this performs basically just as good as a 4-layer board of the same density. (You can just place things closer together on 4L because you aren't wasting space on ground fill and trace routing.)
6 layers, you could have three planes, but symmetry is preferred (unbalanced copper areas can warp the board) so it's often used as "4 layer plus", more routing layers offering easier routing or better signal quality.
8 layers, you can have for example 2 x GND, VDD_IO and VDD_PERIPH say. Which might be, like, an FPGA routing to memory on one supply, also routing say PCIe lanes on the other supply, in the same place so you can't just stitch one supply around the other.
This and up, is probably well outside your scope, but you get the idea. Prioritize supplies by region, usage and requirement (local, lots of VDD pin count, low noise, high current?), and trace-route whatever's left.
So of course on 2-layer, following this scheme, VDD has to be hand routed, and you should prefer more bypass caps as a result -- because again, trace length is inductance, so you don't want to have too much between components, and you also don't want too much length between bypass caps, because they can resonate with each other as well. More generally, there's PDN (power distribution network) analysis, a topic unto itself, but a simple takeaway is, it's better to have bypass caps more or less regularly spaced, than to have long naked trace lengths with big caps at the end. Point-to-point routing can be better than star routing a supply. (But hey, it depends, widely. You can SPICE it, if nothing else!)
Tim