Electronics > PCB/EDA/CAD
Feeding Split planes
AlfBaz:
Hi all,
I'm setting up split planes on a board with high speed signals where Singnal integrity, impedance matching and EMC/EMI have to be taken into account.
A couple of the regions serve only to power core and miscellaneous functions on a 296 ball BGA MCU, whilst others such as DDR controller and IO/COMS are extended to those external devices and are large enough to accomodate a routing path for their respective signals.
I'm wondering if anybody has experience or knowledge of wether it would be better to extend the smaller planes back to their respective power supplies, therefore limiting or interrupting the power plane for other signals or just running chunky traces to them and stitching them with vias.
I'm designing a six layer board with the following stack-up
Top layer
Core
Gnd Plane
Prepreg
Mid-layer1
Core
Split Power Plane
Prepreg
Mid-layer2
Core
Bottom layer
Thanks
free_electron:
Swap power and mid2 to begin....
Signal, gnd , signal signal, power , signal
Ddr should stay on one layer and not go on inner layers.
Do the fan out of the bga and use the inner routing layers around the bga as additional plane area's. If the cpu has a supply that is for it only, like a core voltage, that supply should be close.
Most of the time you can get away by running a 3.3 plane and use local power islands close to the chip.
If you have high speed signals that need to swap layers a ground via should be plugged closeby to provide a return path. Flood the unused space on midlayers with additional ground.
Without knowing more about the design ( what cpu and pinout and what buses.. Usb ? Pcix ? Speed of dram etc ) it is hard to give more info ...
AlfBaz:
Sorry for taking so long to respond and thank you very much for your input
--- Quote from: free_electron on June 18, 2012, 12:37:00 pm ---Swap power and mid2 to begin....
Signal, gnd , signal signal, power , signal
--- End quote ---
What would be the effects of this change to "typical" impedances, given tracks of similar length on the mid-layers or am I missing the point entirely?
--- Quote ---Ddr should stay on one layer and not go on inner layers.
--- End quote ---
I've tried a few scenarios with this and it seems unavoidable for some of the tracks, especially fanning out from the BGA
--- Quote ---Do the fan out of the bga and use the inner routing layers around the bga as additional plane area's. If the cpu has a supply that is for it only, like a core voltage, that supply should be close.
Most of the time you can get away by running a 3.3 plane and use local power islands close to the chip.
--- End quote ---
Are you suggesting to avoid splitting planes at all costs? I'm finding it difficult to afford any space around the BGA chip for routing space let alone power planes.
--- Quote ---If you have high speed signals that need to swap layers a ground via should be plugged closeby to provide a return path. Flood the unused space on midlayers with additional ground.
--- End quote ---
I seem to recall reading this somewhere. Just to make sure I understand what you mean, place a via to ground near the via that changes layers?
--- Quote ---Without knowing more about the design ( what cpu and pinout and what buses.. Usb ? Pcix ? Speed of dram etc ) it is hard to give more info ...
--- End quote ---
Sorry I didn't want to come accross as a bore
The cpu is an LPC3250 which can run at upto 266MHz. I'm going for a variable core voltage to take advantage of power savings in some of the slower modes it can do but some of the pins will also require a fixed 1.2V and the others can go down to 0.9V, so thats essentially two different power nets.
All up I need 3.3V, 2.6V, 1.2V and 0.9/1.3V
Memory is 16bit DDR with a max speed of 167MHz at 2.6V with very short flight times given sub-nanosecond access times (eek)
I'm also implementing nand flash, USB 2.0, 100Mbit ethernet and 24bit LCD
I'm just a hobbyist biting off far more than I can chew, but I'm finding it very interesting.
Thanks again for your time
free_electron:
--- Quote from: AlfBaz on June 19, 2012, 07:51:51 pm ---Sorry for taking so long to respond and thank you very much for your input
--- Quote from: free_electron on June 18, 2012, 12:37:00 pm ---Swap power and mid2 to begin....
Signal, gnd , signal signal, power , signal
--- End quote ---
What would be the effects of this change to "typical" impedances, given tracks of similar length on the mid-layers or am I missing the point entirely?
--- Quote ---
that entirely depends on your layer stack...
by changing the order like i suggest you can pull a trick where you do
--- Code: ---top layer
4 mil prepreg
plane
4 mil prepreg
routing
32 mil core
routing
4 mil prepreg
plane
4 mil prepreg
routing
--- End code ---
This creates two coupled planes with tracks above and below. the distance between the routing inside is 32 mils . given traces of 6 mils this gives you more than the required 3x to avoid garbage. ( for a given track width a distance of 3x provides enough barrier to no longer have perceptible crosstalk . ) you if you were to route with 4 mils ( which should be what you are doing because of the bga ) you have 8x ...
scatter bypass caps at the perimeter and inside to bridge the power and ground plane.
--- Quote ---Are you suggesting to avoid splitting planes at all costs? I'm finding it difficult to afford any space around the BGA chip for routing space let alone power planes.
--- Quote ---
You need to provide a local power island. use bottom layer to create the power planes.
--- Quote ---I seem to recall reading this somewhere. Just to make sure I understand what you mean, place a via to ground near the via that changes layers?
--- End quote ---
correct. also remove unused copper features on inner layer. like the ring around a via. if no connection is required on the layer the pad needs to be deleted.
--- Quote ---Sorry I didn't want to come accross as a bore
--- End quote ---
this kind of design requires lots of information. there is no 'gunshot' approach ...
read AN10778
i don't know your experience level , but this is not an easy chip to work with ... make sure to doublecheck your memory selection. try to find schematics and appsnotes that show schematics with known good chips in them . especially the memory is picky for these things...
What do you use for layout tool ? if you got the pcb in altium ( pcb + netlist ) i can see if i can come up with a breakout strategy for power.
--- End quote ---
--- End quote ---
--- End quote ---
--- End quote ---
AlfBaz:
--- Quote ---
that entirely depends on your layer stack...
by changing the order like i suggest you can pull a trick where you do
--- Code: ---top layer
4 mil prepreg
plane
4 mil prepreg
routing
32 mil core
routing
4 mil prepreg
plane
4 mil prepreg
routing
--- End code ---
This creates two coupled planes with tracks above and below. the distance between the routing inside is 32 mils . given traces of 6 mils this gives you more than the required 3x to avoid garbage. ( for a given track width a distance of 3x provides enough barrier to no longer have perceptible crosstalk . ) you if you were to route with 4 mils ( which should be what you are doing because of the bga ) you have 8x ...
--- End quote ---
Interestingly enough I chose the original stack in an attempt to achieve something along the lines of what you are describing, but I can see that your method makes more sense. As for track width I was planning on using 6mils as I’m limiting to one track between vias/pads in the BGA. As for the 3x/8x you speak of, I’m a little confused as I thought it would be the other way around. Are you saying that with 6mils the distance between two adjacent tracks should be 3x 6mils and with 4 mils, 8x. If this is correct is it because the less width the track has the less it couples to the plane, therefore having to increase distance between tracks to avoid coupling between them?
If this is the case and I can get away with 6mils then wouldn’t this be a better strategy for space saving, given 2 parallel tracks would be 6+(3x6)+6=30 as opposed to 4 mils which would be 4+(4x8)+4 = 40mils
--- Quote ---scatter bypass caps at the perimeter and inside to bridge the power and ground plane.
...
You need to provide a local power island. use bottom layer to create the power planes.
--- End quote ---
Yes, I’ve done this... I’m using 0603 caps and can only fit 2 of them on the inside. The bottom layer for power planes is a good idea as that is where all my bypass caps live
--- Quote ---correct. also remove unused copper features on inner layer. like the ring around a via. if no connection is required on the layer the pad needs to be deleted.
--- End quote ---
Excellent, just the other day I saw somebody asking how to do this on AD10 to get more space/clearance on layers where no connection was made and was planning to implement full stack edits of vias for the BGA fan out. I presume you’re also saying these act as radiating antenna?
--- Quote ---
this kind of design requires lots of information. there is no 'gunshot' approach ...
read AN10778
--- End quote ---
That AN number looked familiar, sure enough it’s a document I have being referring to, one of many that I have downloaded for the LPC3250
--- Quote ---i don't know your experience level , but this is not an easy chip to work with ... make sure to doublecheck your memory selection. try to find schematics and appsnotes that show schematics with known good chips in them . especially the memory is picky for these things...
--- End quote ---
This is a high priority “TO DO” item. Currently I have selected 2 Micron MT46V64M8P 8 bit DDR SDRAMS configured as 16 bit (lowbyte, highbyte) to give me 64Meg as opposed to one 16bit chip giving me a max of 32Meg.
The compatible example memories they show in the reference manual are based on the data sheets and have not been tested. None of them are 8bit and the ones that are Micron are MT46H... not MT46V... Their reference design shows the use of a single MT46V32M16. Hopefully, after some serious study of data sheets this will translate to compatibility across bit width realms
--- Quote ---What do you use for layout tool ? if you got the pcb in altium ( pcb + netlist ) i can see if i can come up with a breakout strategy for power.
--- End quote ---
Thank you very much. I may take you up on that offer as that’s the tool I’m using.
I did a complete route of the board some time ago (half way through the design) to see if I could do it with the size constraints I gave myself and also to carry out some preliminary signal integrity tests. I have, however nearly completed the design and have now brought out nearly all of the signals, with unused IO, I2C, SPI and RX/TX lines coming out to a board connector for future expandability
I have "unrouted all" and starting fresh
Navigation
[0] Message Index
[#] Next page
Go to full version