Four ground layers stitched together under an Artix-7 FPGA is a bad idea?

[asmi]

So now it is
Top
Sig
GND
Sig
PWR
Bottom

Each signal layer is adjacent to GND

It doesn't seem so to me. What about top and bottom layers? What are they referenced to?
Also - referencing high-speed signals to a power rail is an advanced technique which should only be used by experienced designers who understand what are they doing, as there is a very high risk to screw things up.

Is the fan really justified? My implementation report shows room 25.9 *C temperature but it's only 27-29MHz the image part of it

Absolutely. That report is a classic example of GIGO (garbage in - garbage out) - you provide crap input, it generates crap output. Unless you provide it with realistic input switching data, it won't output anything useful at all.
BTW if you need A200T but running only at 29 MHz, I strongly suspect that you can double the frequency and fit everything into A100T.

[bmxsesh]

So now it is
Top
Sig
GND
Sig
PWR
Bottom

Each signal layer is adjacent to GND

It doesn't seem so to me. What about top and bottom layers? What are they referenced to?
Also - referencing high-speed signals to a power rail is an advanced technique which should only be used by experienced designers who understand what are they doing, as there is a very high risk to screw things up.

Is the fan really justified? My implementation report shows room 25.9 *C temperature but it's only 27-29MHz the image part of it

Absolutely. That report is a classic example of GIGO (garbage in - garbage out) - you provide crap input, it generates crap output. Unless you provide it with realistic input switching data, it won't output anything useful at all.
BTW if you need A200T but running only at 29 MHz, I strongly suspect that you can double the frequency and fit everything into A100T.

There are no signals on top and bottom layers, only power lines
Bottom is copper pours of +5V, 3.3V, 1.8V, 0.95V coming out of DC/DC and power jack to a skip layer (one above bottom) and all power needs of the ICs on the top layer are wired to the vias to this skip layer which is number 5 in the list

[asmi]

There are no signals on top and bottom layers, only power lines

And how your chips are going to be connected to those internal signal layers? Those connections are traces too, and they require the same treatment.

Bottom is copper pours of +5V, 3.3V, 1.8V, 0.95V coming out of DC/DC and power jack to a skip layer (one above bottom) and all power needs of the ICs on the top layer are wired to the vias to this skip layer which is number 5 in the list

I'm sorry but I feel like you've bitten more than you can chew, so here is my final advice - learn a thing or two about high-speed design, trace impedance, transmission lines, before you embark on a project like this for it to avoid being a total failure.

[forrestc]

There are no signals on top and bottom layers, only power lines
Bottom is copper pours of +5V, 3.3V, 1.8V, 0.95V coming out of DC/DC and power jack to a skip layer (one above bottom) and all power needs of the ICs on the top layer are wired to the vias to this skip layer which is number 5 in the list

I'm not sure you're fully understanding the goal with the ground layers.  I posted a link to the video at

which is a pretty in depth introduction but does have a fair bit of advanced terminology.  I still recommend watching all of it.    After digging a bit, it seems like the first half of the video at

should also be useful.

With modern design power lines ARE signal lines.  Every clock transition in the FPGA requires a change in current on the power distribution network.  As a result, even power lines need a reference ground layer.   You should treat the power distribution network no differently than high-speed signals, except for, of course, paying attention to issues related to high currents flowing through the traces.   

Because of this, your top 3 layers, should almost certainly be:

Signal  (this is the outside layer)
GND 
Signal

As much as possible should be routed in these three layers.  If at all possible, run your differential pairs and highest speed signals on the outside two rows of pins on the FPGA so that they don't have to be pushed down to the inner layers.  Any that won't fit on the top layer can go onto layer #3 or another layer.   Note that routing power on these layers is fine as well, but critical signals should be prioritized on these layers.   One thing to mention is that to some extent the thickness of the pcb material (prepeg/core) will influence which layers are most tightly coupled to their ground plane - layer 1 and 2 will be coupled tightly, layer 3 tends to be further away from layer 2 than layer 1 is so layer 3 doesn't do quite as good of job with high speed signals.