Four ground layers stitched together under an Artix-7 FPGA is a bad idea?

[bmxsesh]

I'm reading that ideally there is one uninterrupted copper sheet as a ground reference for all components. But it would be difficult for me to do since the layout I chose is:
Top
+5V
GND
Signal
+3.3V
GND
Signal
+1.8V
GND
Signal
+0.95V
GND
Signal
Bottom - 13 layers total. DC/DC converters and decoupling is on the bottom under the FPGA chip. PWR_OK led and DONE_PROG led are on the top side.

All signals go to the breakout pins to off-board circuits. So I guess the return path for these signals is from that supply GND pin. This is only a breakout board for some 134 IO'S
Now I would say it would be impossible for me to do an uninterrupted internal layer since some of the I/Os are via-in-the-pad drilled through the thickness of the entire board to the bottom side. So the only option would be the copper pour on the bottom as GND.
So all this on a screenshot is a 3 cm x 3 cm(27mm x 27 mm FBG676 BGA chip) henceforth 9cm^2 x 4 that's four 9cm^2 metal sheets stitched together with buried vias. Could that lead to some problems (I am intending this for a ~30MHz project)

[nctnico]

Stitching ground planes together isn't a problem. However, to me this seems like a really bad stackup and poor use of 13 layers.

If the design is just a break-out board then 8 layers should be more than enough to also support using high speed signals:
1 signal 1/ top
2 ground
3 signal 2
4 ground
5 power 1
6 power 2
7 ground
8 signal 3/ bottom

You always want to have power planes sandwiched between grounds and signals should also be referenced to ground, not power. For low speed signals, you could resort to using free space on the power 1 and power 2 layers giving more flexibility.

With a bit of creativity, a 4 layer board could be sufficient as well if you can route all signals to the breakout connectors on the top layer, use 1 ground plane and use 2 layers for extra signals and power.

[thm_w]

30MHz is not that high, but, you still only have 1 ground pin for 100+ IO?
Doesn't seem ideal.

https://electronics.stackexchange.com/questions/207752/how-many-ground-and-power-pins-to-have-in-a-connector

[nctnico]

30MHz is not that high, but, you still only have 1 ground pin for 100+ IO?
Doesn't seem ideal.

https://electronics.stackexchange.com/questions/207752/how-many-ground-and-power-pins-to-have-in-a-connector

That is a good catch indeed! I didn't even look that far. Not having a whole bunch of ground pins is the number one mistake people make when designing breakout / add-on boards. And besides having ground pins, also make sure to have grounded mounting holes so metal standoffs can be used to connect ground of a carrier board to the add-on board.

Having some TVS diodes and/or series resistors on the programming signals might also be a good idea just to make sure the FPGA isn't damaged by ESD or half the AC mains coming from a non-grounded mains adapter.

[Sensorcat]

There is a discrepancy between your layer list in text (12 items between top and bottom) and in screenshot (11 inner layers). Also, what is a '30MHz project?'. Since this is no standard nomenclature, it is important to clarify what that means. Is the highest component of any signal in the project 30MHz? Or do you need a clean 30MHz square wave for the project to operate properly? In the latter case, well-controlled transfer of 300MHz signal components (harmonics of the square) is the bare minimum.

[bmxsesh]

30MHz is not that high, but, you still only have 1 ground pin for 100+ IO?
Doesn't seem ideal.

https://electronics.stackexchange.com/questions/207752/how-many-ground-and-power-pins-to-have-in-a-connector

That is a good catch indeed! I didn't even look that far. Not having a whole bunch of ground pins is the number one mistake people make when designing breakout / add-on boards. And besides having ground pins, also make sure to have grounded mounting holes so metal standoffs can be used to connect ground of a carrier board to the add-on board.

Having some TVS diodes and/or series resistors on the programming signals might also be a good idea just to make sure the FPGA isn't damaged by ESD or half the AC mains coming from a non-grounded mains adapter.

I think there is some ESD protection within the FPGA.
Programming is done in two steps. First the SPI Flash chip is programmed with something like a Raspberry Pi computer at the bottom six pins. The rest of the board is not powered. Then the SPI lines are shorted and the flash becomes one with the rest of the circuit. Now the entire board is powered from +5V jack and the FPGA reads its bitcode from the Flash memory. PWR_OK lights up when 3.3V rail is operational. DONE lights up when the DONE pin is released from low to high by the FPGA and indicates that the bitcode was read succesfully. There's no JTAG involved.

There is a discrepancy between your layer list in text (12 items between top and bottom) and in screenshot (11 inner layers). Also, what is a '30MHz project?'. Since this is no standard nomenclature, it is important to clarify what that means. Is the highest component of any signal in the project 30MHz? Or do you need a clean 30MHz square wave for the project to operate properly? In the latter case, well-controlled transfer of 300MHz signal components (harmonics of the square) is the bare minimum.

There are two clocks 27 MHz is 1.8V silicon oscillator and 29.5MHz 3.3V resistor set oscillator. Microchip and LTC respectively. The signals will go off the board/come from off-board circuits via the breakout pins. I have signals changing layers through vias from a microstrip to a 0.08mm wire like you can see in the screenshot, but at the very end it goes through the 2.54mm plated hole to a standard rainbow colored wire, and this is the impedance I won't be able to control. I will think what can be done with the power line size

Full project is at github.com/mbondaru/flasher if you have access to Linux and LibrePCB

[Psi]

Are you using buried/blind vias?  I've seen people try to use a massive number of layers because it had not occurred to them that using buried/blind vias would help and reduce layer count.
Another thing people somethings forget is to turn off the thing that always creates pads around vias on layers where you don't need to connect to the via. By removing those pads it gives you more room to route other tracks.

(Apologies if you know this all already, I was just checking because 13 is a lot of layers).

[bmxsesh]

Are you using buried/blind vias?  I've seen people try to use a massive number of layers because it had not occurred to them that using buried/blind vias would help and reduce layer count.
Another thing people somethings forget is to turn off the thing that always creates pads around vias on layers where you don't need to connect to the via. By removing those pads it gives you more room to route other tracks.

(Apologies if you know this all already, I was just checking because 13 is a lot of layers).

My local PCB fab can make some 24 layers so it doesn't seem like a big deal. There is just a lot routed and can only be routed under the FPGA BGA chip.
It needs three voltage levels (1.8V and 3.3V IO banks, 0.95V core voltage), ground, that's already 4. DC/DC converters are directly beneath the FPGA to save space for tracks, so the power supply +5V inner layer is also under the FPGA, that's 5 layers already. Then every signal that is not on the edge of the package is routed through a via to one of three inner signal layers 3,6, and 9. That's makes 8 inner layers required under the 676 pin BGA FPGA chip. Some I/Os have a via-in-the-pad drilled through the thickness of the entire board to a wire on the opposite side of the deck. This is my first time making a PCB of this complexity and in fact the first time making a PCB at all

The only buried vias are the stitching ones that stitch together four ground layers 2, 5, 8, and 11 all around the BGA chip. The rest is blind vias from surface to some inner layer.

The green circle on the screenshot is a through-hole via from Top to Bottom. The circles around them are clearance pads that don't let these vias short with the 3.3V layer (big metal sheet) that they are passing through, in my understanding. Is that what you are talking about?

30MHz is not that high, but, you still only have 1 ground pin for 100+ IO?
Doesn't seem ideal.

https://electronics.stackexchange.com/questions/207752/how-many-ground-and-power-pins-to-have-in-a-connector

Using this website's guidelines: https://resources.altium.com/p/pcb-trace-width-vs-current-table-high-voltage-design
The DC/DC converters that supply 3.3V and 1.8V that goes off board can supply 3A of current at most per channel. So I need 50 mil or 1.27 mm wide power trace to off-board circuits, both power and ground. Breakout through hole diameter is 1 mm (see screenshot 2). So one such pair of pins PWR/GND can practically deliver almost all of the 3A that DC/DC converter can provide. The power goes from 18 μm thick 2 mm wide copper foil to a much thicker wire so I don't know if more is really needed
Converters are LTC3633 and LTC3621

[thm_w]

My concern with a single GND pin is not related to DC current capacity, its to do with signal integrity.

[bmxsesh]

My concern with a single GND pin is not related to DC current capacity, its to do with signal integrity.

So here I have a 14-bit 120MHz DAC, AD9744. It only seems to have one or at most two ground legs. Why it doesn't need a ground leg for each signal line like the guy from stackexchange suggests that you posted? I'm a bit falling behind on theory here. It's obviously not a huge PCB, only a small silicon chip, but still

[forrestc]

The DC/DC converters that supply 3.3V and 1.8V that goes off board can supply 3A of current at most per channel. So I need 50 mil or 1.27 mm wide power trace to off-board circuits, both power and ground.

As thm_w mentioned, when moving high speed signals across a connector you need to add ground pins for signal integrity.  At the bare minimum,  you want 1 pin for every 3 signal pins, in an arrangement like this:

Code: [Select]

SSSGSSSGSSSGSSSGSSSGSSSG
SGSSSGSSSGSSSGSSSGSSSGSS

That way every pin is able to have a ground reference next to it.   Even better is moving to an alternating S/G pattern (so every signal is next to 3 ground pins) or even swapping the S's and the G's in the example, so every signal is completely surrounded by ground pins.

As far as the stackup goes on 6 layers and above boards, the top 3 layers should almost always be Sig-GND-SIG.   This gives you two layers referenced to a single ground layer.   I almost always put my "used by almost everything" power layer as layer 4 followed by and additional GND on layer 5, and then the rest I assign depending on what I'm doing with the board.   If it was all signals I'd just alternate sig/gnd, and for many additional power busses, I just treat them as another signal.   So for many of my designs it would be SIG-GND-SIG-PWR-GND-SIG/PWR-GND-SIG/PWR (and so on with more GND-SIG/PWR alternates)

I highly recommend the following useful video (which is really more of a free webinar): 

 

This video is a very good introduction to grounding and signal integrity and will help greatly with understanding why at least a couple of us are pointing out certain potential issues here.  It will also help you understand the desire for a single uninterrupted ground plane.

[forrestc]

So here I have a 14-bit 120MHz DAC, AD9744. It only seems to have one or at most two ground legs. Why it doesn't need a ground leg for each signal line like the guy from stackexchange suggests that you posted? I'm a bit falling behind on theory here. It's obviously not a huge PCB, only a small silicon chip, but still

Because the part was released in 2002 before we understood signal integrity as well as we do?  Remember the 7400 series had power and ground at opposite corners which is horrible.   And yes, even newer parts have horrible pinouts for signal integrity.  One thing that always comes up when discussing signal integrity among people who know what is going on is why do the IC designers still insist on giving board designers pinouts that are atrocious.   Note that to some extent the answer is that at the scale of a chip, and especially if you have a grounded substrate or exposed pad, it isn't that much of a problem.  Adding a copper pour under the IC itself can help, but I don't know how much that is needed on a board with a ground plane on layer 2.

Note that many (if not most or all) recently released BGA fpga's have a pinout which ensures that every i/o pin is next to a ground pin.

[Smokey]

The world has become an amazing place when you even consider making 12 layer boards just because....

[exmadscientist]

Some other people have been dancing around this but I am going to come right out and say it: I think you have bitten off more than you can chew and you should probably not be attempting this project as your first PCB.

You should really know why 13 layers is not possible. Ever. (Yes, some vendors will quote it, blah blah blah, some might even do it... but the quotes are f-off quotes and the boards will fail early if anyone is dumb enough to build them for any reason short of total desperation.) To get 134 I/Os out of a 676-ball BGA is not very difficult. You can probably do this in 4 layers if you are clever and patient; 6 is probably not too hard at all; and 8 should yield an excellent electrical and physical design, executed quickly, for the modest unit cost increase. (So, what I'm saying is, start with 8.) The only thing that should give you real pause is the fanout, as you do mention... but it's an FPGA so you can just put everything on the outer two rows (there's ~200 balls there!), where no vias are needed to break out, or at least you can break it all out however it needs to go to be nice and clean.

Your design rules may even permit vias directly between pads, at 1mm pitch. (1mm pitch is easy mode.) Or you can probably get three traces between pads. This is what makes these things possible.

I think there is some ESD protection within the FPGA.

There is not. Or, at least, there is little enough that you will be happier pretending there is not. Protect all off-board signals if you want your chips to live!

My concern with a single GND pin is not related to DC current capacity, its to do with signal integrity.

So here I have a 14-bit 120MHz DAC, AD9744. It only seems to have one or at most two ground legs. Why it doesn't need a ground leg for each signal line like the guy from stackexchange suggests that you posted? I'm a bit falling behind on theory here. It's obviously not a huge PCB, only a small silicon chip, but still

They can get away with this for ICs because ICs are tiny and sometimes even have onchip decoupling. You (and I) cannot get away with this for connectors. Connectors are hell, electrically, mechanically, and every other way. Your precious signals need their figurative hands held every step of their journeys off board, or they will suffer, and your reputation will suffer for it.

You may want to post your schematic here (as a PDF! or PNG! or whatever that isn't proprietary to your software!) for comment (probably in another thread). Someone might be able to save you a spin or three.

[bmxsesh]

Some other people have been dancing around this but I am going to come right out and say it: I think you have bitten off more than you can chew and you should probably not be attempting this project as your first PCB.

You should really know why 13 layers is not possible. Ever. (Yes, some vendors will quote it, blah blah blah, some might even do it... but the quotes are f-off quotes and the boards will fail early if anyone is dumb enough to build them for any reason short of total desperation.) To get 134 I/Os out of a 676-ball BGA is not very difficult. You can probably do this in 4 layers if you are clever and patient; 6 is probably not too hard at all; and 8 should yield an excellent electrical and physical design, executed quickly, for the modest unit cost increase. (So, what I'm saying is, start with 8.) The only thing that should give you real pause is the fanout, as you do mention... but it's an FPGA so you can just put everything on the outer two rows (there's ~200 balls there!), where no vias are needed to break out, or at least you can break it all out however it needs to go to be nice and clean.

Your design rules may even permit vias directly between pads, at 1mm pitch. (1mm pitch is easy mode.) Or you can probably get three traces between pads. This is what makes these things possible.

I think there is some ESD protection within the FPGA.

There is not. Or, at least, there is little enough that you will be happier pretending there is not. Protect all off-board signals if you want your chips to live!

My concern with a single GND pin is not related to DC current capacity, its to do with signal integrity.

So here I have a 14-bit 120MHz DAC, AD9744. It only seems to have one or at most two ground legs. Why it doesn't need a ground leg for each signal line like the guy from stackexchange suggests that you posted? I'm a bit falling behind on theory here. It's obviously not a huge PCB, only a small silicon chip, but still

They can get away with this for ICs because ICs are tiny and sometimes even have onchip decoupling. You (and I) cannot get away with this for connectors. Connectors are hell, electrically, mechanically, and every other way. Your precious signals need their figurative hands held every step of their journeys off board, or they will suffer, and your reputation will suffer for it.

You may want to post your schematic here (as a PDF! or PNG! or whatever that isn't proprietary to your software!) for comment (probably in another thread). Someone might be able to save you a spin or three.

This is what a 0.08mm trace looks like between 1.0mm BGA balls. I don't know what three wires you are telling me about, one already seems to short with the ball land copper. At least the way my software generates BGA balls, it doesn't seem I can route any wires between inner pads. My manufacturer requires to make tear-shaped BGA lands for easier soldering control
FPGA vendor AMD Xilinx does mention it is 2 or 4 layers for 676 pin BGA but look at the screenshot it is sketchy to lay a wire like this. It is the thinnest wire I can lay. I am not using wires on inner layers, only microstrips or striplines like I posted above with a via transition to a surface wire

[exmadscientist]

You're right that you can't get three traces through (at least at 75µm trace/space), I was off by one (should never have learned how to do software! never!) but the rest is all true, see the attached.

You'll need slightly smaller pads than the usually recommended 0.6mm, but with NSMD pads slightly smaller is often good anyway, and I doubt you're going to HVM with this thing so it should be fine. Yes, some of those things need 75µm trace/space (which manufacturers will usually do for you if you keep it constrained to a BGA fanout zone), VIPPO (via-in-pad-plated-over; this is rapidly getting common and has been common in HVM for ages), or even laser drills (still less common for LVM but, again, everywhere in HVM) but... you can do it. Laser microvias may be the hardest thing to achieve here and they are only needed if you must have vias outside of the usual "checkerboard offset" BGA pattern.

Your pad shape looks wrong which is no doubt part of your problems. I don't know why you would want asymmetrical pads like that. Your manufacturer is kind of strange, do they not have an x-ray inspection system or something? You probably don't want them doing prototypes of a 676-ball BGA without x-ray inspection. What are the actual pad dimensions you are using/they are asking for?

[bmxsesh]

You're right that you can't get three traces through (at least at 75µm trace/space), I was off by one (should never have learned how to do software! never!) but the rest is all true, see the attached.

You'll need slightly smaller pads than the usually recommended 0.6mm, but with NSMD pads slightly smaller is often good anyway, and I doubt you're going to HVM with this thing so it should be fine. Yes, some of those things need 75µm trace/space (which manufacturers will usually do for you if you keep it constrained to a BGA fanout zone), VIPPO (via-in-pad-plated-over; this is rapidly getting common and has been common in HVM for ages), or even laser drills (still less common for LVM but, again, everywhere in HVM) but... you can do it. Laser microvias may be the hardest thing to achieve here and they are only needed if you must have vias outside of the usual "checkerboard offset" BGA pattern.

Your pad shape looks wrong which is no doubt part of your problems. I don't know why you would want asymmetrical pads like that. Your manufacturer is kind of strange, do they not have an x-ray inspection system or something? You probably don't want them doing prototypes of a 676-ball BGA without x-ray inspection. What are the actual pad dimensions you are using/they are asking for?

All they say is that the teardrop-shaped pad makes the solder obtain a specific shape that helps with the x-ray inspection
Everything else in terms of dimensions I only get from the official specs (see the screenshot)
Yes my maximum limits are 0.075 mm wide trace and 0.075 mm copper to copper
I did make a 0.6 mm pad as per specs

[bmxsesh]

You're right that you can't get three traces through (at least at 75µm trace/space), I was off by one (should never have learned how to do software! never!) but the rest is all true, see the attached.

You'll need slightly smaller pads than the usually recommended 0.6mm, but with NSMD pads slightly smaller is often good anyway, and I doubt you're going to HVM with this thing so it should be fine. Yes, some of those things need 75µm trace/space (which manufacturers will usually do for you if you keep it constrained to a BGA fanout zone), VIPPO (via-in-pad-plated-over; this is rapidly getting common and has been common in HVM for ages), or even laser drills (still less common for LVM but, again, everywhere in HVM) but... you can do it. Laser microvias may be the hardest thing to achieve here and they are only needed if you must have vias outside of the usual "checkerboard offset" BGA pattern.

Your pad shape looks wrong which is no doubt part of your problems. I don't know why you would want asymmetrical pads like that. Your manufacturer is kind of strange, do they not have an x-ray inspection system or something? You probably don't want them doing prototypes of a 676-ball BGA without x-ray inspection. What are the actual pad dimensions you are using/they are asking for?

This is what I got now: three different footprints for a BGA pad
Now the smallest one at the minimum spec does allow to carefully lay a wire that is conforming to 0.075 mm clearance + 0.075 mm wire width + 0.075 mm clearance
In my initial layout I sticked with NOM. dimensions of the datasheet from a previous post but this now is pretty much the MIN. that is allowed
Last screenshot is how much space I had originally
Only I don't know if this change will help with manufacturing but laying out does become slightly easier

[bmxsesh]

The world has become an amazing place when you even consider making 12 layer boards just because....

See screenshot, but also depends on how densely you want to place the components, board size may matter for some applications and this is where layers are useful
40% of this BGA is power and ground pins, 0.95V, 1.8V and 3.3V scattered all over the chip
This comment was not useful at all, I'm sorry

My concern with a single GND pin is not related to DC current capacity, its to do with signal integrity.

I'm thinking KVL and KCL and this theory doesn't make much sense to me
Some transient inductive currents due to self-inductance of the trace? How bad are they?

[bmxsesh]

https://indico.cern.ch/event/926254/contributions/3906671/attachments/2107923/3545197/Powering_large_FPGAs.pdf
See page 10 the stackup for large FPGA
Their definition of Large is 240-320 decoupling caps, mine is over 150 capacitors already
I'm sorry this has turned into an argument about layers not electricity

[Smokey]

Lets say you make a 20 layer board, and use use optimal design rules for all the routing.  Do you have the equipment and test setups to measure if that made any difference over something like a 4 layer board with poor routing assuming both design appear to be "working"?  What is the performance spec you are trying to hit and how will you verify that?

If the goal here is to make what looks like a 0.1in header breakout board for an FPGA, and those signals are run off through ribbon cables or something (with minimal cabling grounding as noted elsewhere), the actual PCB layout will probably not be the limiting factor for high speed signals getting where they are going.

A note about high speed cabling. Look at something like HDMI.  There is a ground pin for each set of differential pairs.  Every high speed signal has it's own ground reference pin on the cable.

[bmxsesh]

Lets say you make a 20 layer board, and use use optimal design rules for all the routing.  Do you have the equipment and test setups to measure if that made any difference over something like a 4 layer board with poor routing assuming both design appear to be "working"?  What is the performance spec you are trying to hit and how will you verify that?

If the goal here is to make what looks like a 0.1in header breakout board for an FPGA, and those signals are run off through ribbon cables or something (with minimal cabling grounding as noted elsewhere), the actual PCB layout will probably not be the limiting factor for high speed signals getting where they are going.

A note about high speed cabling. Look at something like HDMI.  There is a ground pin for each set of differential pairs.  Every high speed signal has it's own ground reference pin on the cable.

Shrinking ball size did help with layers. I am now at 7 layers:
1) Top (power pins routed from underneath FPGA and decoupling capacitor network)
2) Sig (differential, for Ethernet)
3) Sig (1.8V, 3.3V CMOS)
4) GND - one 0V reference for all circuits
5) Sig (DC converter cables that didn't fit on the bottom side)
6) PWR (+1.8V , +3.3V, +0.95V FPGA voltages)
7) Bottom (copper pours of 4 voltage levels +5V +3.3V +1.8V and 0.95V feeding straight into DC/DC converters)
The good news is that all planes are adjacent and not penetrated thus no more "swiss cheese" metal sheets
8mm wide return path for all power and signals back to the power source

[asmi]

You don't need to have entire layer for each power rail, because people designing FPGA pinout thought about it and designed pinout in such a way that you can use a single layer for all Vccio rails. Here is my board with Artix-100T: https://www.eevblog.com/forum/fpga/planningdesignreview-for-a-6-layer-xilinx-artix-7-board-for-diy-computer/msg5134983/#msg5134983 It's a 10 layer PCB, and it's got a single power layer with all Vccio rails implemented as planelets. Attached is the stackup I used for that board.

[asmi]

1) Top (power pins routed from underneath FPGA and decoupling capacitor network)
2) Sig (differential, for Ethernet)
3) Sig (1.8V, 3.3V CMOS)
4) GND - one 0V reference for all circuits
5) Sig (DC converter cables that didn't fit on the bottom side)
6) PWR (+1.8V , +3.3V, +0.95V FPGA voltages)
7) Bottom (copper pours of 4 voltage levels +5V +3.3V +1.8V and 0.95V feeding straight into DC/DC converters)

That's the worst stackup I have ever seen You need to have a reference for each signal layer. See the stackup I used for example of proper stackup.
Also, I would highly recommend to do some study of high-speed design, what is trace impedance, why it's important, how to properly route high-speed signals, etc., as the offered stackup shows that you sorely lack the knowledge in this area.

[bmxsesh]

My bad. I thought the differential signaling doesn't need a reference to GND plane, but it actually does. So signal wise I have

Sig
GND
Sig

So two signal layers referenced to the only 0V sheet

1) Top (power pins routed from underneath FPGA and decoupling capacitor network)
2) Sig (differential, for Ethernet)
3) Sig (1.8V, 3.3V CMOS)
4) GND - one 0V reference for all circuits
5) Sig (DC converter cables that didn't fit on the bottom side)
6) PWR (+1.8V , +3.3V, +0.95V FPGA voltages)
7) Bottom (copper pours of 4 voltage levels +5V +3.3V +1.8V and 0.95V feeding straight into DC/DC converters)

That's the worst stackup I have ever seen You need to have a reference for each signal layer. See the stackup I used for example of proper stackup.
Also, I would highly recommend to do some study of high-speed design, what is trace impedance, why it's important, how to properly route high-speed signals, etc., as the offered stackup shows that you sorely lack the knowledge in this area.

So now it is
Top
Sig
GND
Sig
PWR
Bottom

Each signal layer is adjacent to GND

My application did not fit on a 100T chip so I had to pick 200T
It is a parallel image processor (headless)
Is the fan really justified? My implementation report shows room 25.9 *C temperature but it's only 27-29MHz the image part of it