EEVblog Electronics Community Forum
Electronics => PCB/EDA/CAD => Topic started by: Rat_Patrol on February 03, 2020, 08:47:14 pm
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I designed a board in Sprint-Layout some years ago, back when I first started designing my own PCBs. It has gotten more and more complicated as I had revisions and improvements, and is now a 4 layer PCB of 150x200mm in size. None of this was done with schematics at all, just adding components and tying it into the circuitry as it needed to be.
At this point, I would like to refine the design and have a regular schematic so I can completely re-work the PCB layout w/o starting from complete scratch of the now complicated circuitry. In essence, I need to reverse-engineer my own work!
Since Sprint-Layout doesn't deal with netlists or schematics, just simply drawing circuits, is there a way to use the gerber files Sprint-Layout generates in Eagle/KiCad (2 programs I use now) or another to create a schematic?
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Since Sprint-Layout doesn't deal with netlists or schematics, just simply drawing circuits, is there a way to use the gerber files Sprint-Layout generates in Eagle/KiCad (2 programs I use now) or another to create a schematic?
Not really. My experience is mainly KiCad, it's possible latest version of Eagle have features I'm not aware of. You could import the gerbers as a graphic into a PCB layer and use that as a template to draw over, placing footprint and tracks. But that doesn't get you a netlist or schematic.
In theory you could write a script to read the gerbers and generate a PCB layout with the tracks, leaving the user to place footprints. Automatically identifying footprints from the gerbers is not trivial.
My advice is that unless it is something worth paying a third party company to do, it is better to create a schematic from scratch.
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Cannot agree more. Even if there was a schematic generated from the gerbers and BOM it would still be not very logical. Redraw from memory is the best option here...
Let us not allow the AI algorithms to overtake us humans...
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You can do this sort of thing in altium's CAM tool (atleast extract a netlist from physical copper). You would either need to manually define packages in CAMtastic to have a netlist that also include designator and pin notation.
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Think of Gerber files as essentially containing instructions for a plotter to draw trace segments and pads. The files do not contain the information which pads belong together (as part of one component or chip), let alone the chip's function. And they don't even tell you whether a trace segment is "connected" to a pad or another trace; you have to figure out whether they touch. (At least that part can be automated...)
So no, going back to a schematic from there doesn't really work in any automated fashion. Too much information about the underlying structure is missing in the Gerbers.
Also, this is probably a great opportunity to step back, give the whole circuit some thought, and draw a proper, well-organized schematic! ;)
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The Viewlogic tools I used mid 1990s included a logic (boolean) to schematic generator, for digital logic.
The result wasn't pretty but it was correct.
It was handy for e.g. including a piece of design done in a PLD (and available only as equations) into an FPGA design which was mostly drawn as a schematic.
Never heard of a gerber to schematic converter but you could do it manually...
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With KiCad you can back import Gerbers into Pcbnew, very easily, but it's far from perfect because simply a lot of the information is missing in the gerber files.
What you get is:
* Board outline,
* Placement of mounting holes.
* All the tracks on all the layers.
* SMD pads for all footprints (including original THT components).
* Placement of all the components, (Implicitly in pad locations and track ends).
* Netlist / sort of. (Read on).
As I said, far from perfect, but much better then nothing.
The second step is to remove the loose pads, and put real footprints from KiCad's library on the ends of the tracks.
This will of course generate lots of DRC errors, because there is no netlist to work with.
So the next step is to draw the schematic in Eeschema (Which you have to do anyway), and then, if you import the netlist into Pcbnew, the DRC errors will disappear , because the existing PCB layout coincides with the newly created netlist.
Realise that this is an iterative process, especially if you are a beginner with KiCad. So start with a small corner of the PCB untill you've figured out how to match loose footprints in PCBnew with schematic symbols.
From Eeschema -> Pcbnew it normally goes with timestamp values, which are useless to you. You need to select "update by Reference", which will match the RefDes (U12, R121, etc).
You also do not have to do the footprint assignment in Eeschema. You can export a Footprint Association File with the footprint info of the footprints you have selected in Pcbnew.