Ground planes on top and bottom? And general PCB layout advice!

[attie]

Hi all,

I'm designing a BLDC speed controller. It has a hefty VBAT pour on the top layer, along side the majority of the signals. I've had a ground plane on the bottom layer since the beginning.
I'm wondering if there are any positives / negatives to having a ground plane on the top and bottom layer. Note that the top ground plane is beside the VBAT pour.

I would also really appreciate any design tips / comments

I know that the design is probably a little complex - I've thrown in a CPLD because I want to play with one, and there is an AVR there for overall control and serial comms to what will one day be a flight computer.

Images:
Top and Bottom
Top only
Top with GND highlighted
Bottom only
Bottom with GND highlighted

Thanks in advance!

Attie

[marshallh]

Looks good. Ground via on the right JP3 is a bit close, you might short it out soldering.
Your bottom ground is relatively contiguous, and I see you have stitching vias connecting the ground pours.

Silkscreen designators are awfully small. Might go into the library package and bump up the text size.

Check your gerbers in this:
http://mayhewlabs.com/webGerber/
Good for checking solder mask as well.

[Kremmen]

You have lots of silk over pads. That is going to be a big grief when soldering this thing so i strongly recommend you fix every instance. You have these nice symbols in the silkscreen, but they are no all that useful, especially if they make soldering troublesome. I don't use Eagle myself, but if there is the option to check silk over pads in the DRC, then by all means turn it on.

It would be useful to see the schematic as well for comparison. There might be issues with the current sense circuits but those are a bit hard to decipher from the layout only.

P.S. there is also an issue with the smoothing caps; they overhang the board which is not a good idea due to lack of mechanical support and also one very narrowly misses interference with a FET. More clearance would be good.

P.P.S. Fixing holes in a row on one side? Why not in the corners or at least on 2 sides. All the mass is now on the unsupported side (the caps) but there would be plenty of room for a couple of holes to support that as well.

[marshallh]

You have lots of silk over pads. That is going to be a big grief when soldering this thing so i strongly recommend you fix every instance. You have these nice symbols in the silkscreen, but they are no all that useful, especially if they make soldering troublesome. I don't use Eagle myself, but if there is the option to check silk over pads in the DRC, then by all means turn it on.

It would be useful to see the schematic as well for comparison. There might be issues with the current sense circuits but those are a bit hard to decipher from the layout only.

P.S. there is also an issue with the smoothing caps; they overhang the board which is not a good idea due to lack of mechanical support and also one very narrowly misses interference with a FET. More clearance would be good.

P.P.S. Fixing holes in a row on one side? Why not in the corners or at least on 2 sides. All the mass is now on the unsupported side (the caps) but there would be plenty of room for a couple of holes to support that as well.

You're actually seeing the tDocu layer which is just for looks, I'm sure OP knows to leave it off when exporting gerbers

[AndyC_772]

Do you have any transient voltage suppressors or clamping diodes to protect your drive transistors from inductive spikes? When the transistors turn off, where's the path for current to keep circulating?

Could you post your schematic showing how the transistors are wired? It looks as though the mounting tab (usually the drain) is connected to the coil for one type, but the source is connected to the coil for the others. In a P channel FET the body diode allows current to always flow from drain to source, so it's worth checking that they're connected the right way round so you can turn them off.

I'd expect to see either the two sources connected together or the two drains, depending on how your output stage is driven.

[attie]

Hi all,
thanks for your comments - much appreciated.

I have regenerated the files taking your notes into consideration.

• marshallh: I have moved the via next to JP3 up and in a bit. I've use this size silk on projects before and it has come out okay... I may bump it up a bit, though I haven't yet. Thanks also for pointing out that I shouldn't be putting the t/bDocu layers into the gerbers... I had most of my text in those layers(!)
• Kremmen: That is indeed the t/bDocu layers showing through, just to help get an idea of what the components might be. The schematic is now included (see links below). I intend to mount the smoothing caps with a 90 degree bend in the leads at or close to the pcb. This will limit the component height and make them as 'flush' as a can can be. The mounting holes are for final use mounting. I intend to 'hang' the an ESC under each arm of a quadcopter to reduce the length of the motor wires. The down draft from the prop will also help with cooling the FETs
• AndyC_772: Not as such. What do you mean by 'transient voltage suppressors'? Is it similar to a snubber (RC to GND)? That is something that I'm considering adding. Do you have any advice for component power ratings? With regard to keeping the current circulating, I was going to activate the low-side FET of the hi coil when PWM is low (if that makes sense). Are the body diodes not enough? And with regard to the FETs, I'm using all N-channel, so hopefully that clears up your confusion.

New info:
PCB
PCB (top)
PCB (top - GND highlighted)
PCB (bottom)
PCB (bottom - GND highlighted)
Schematic (PDF)

Thanks again!

[Kremmen]

OK, fair enough. As i noted i am not that familiar with Eagle so the silk issue seems to be a non-issue . If the caps are that way on purpose then no more need to be said, you know what you are doing. Also the schematic clarifies the sense line questions i had.
The FET substrate diodes should be OK. Qrr is less than 100 nC so unless you are really going overboard with the switching frequency, reverse recovery will not be a problem. Looks like the Irr will be ~0.6 amps so that wont't be a problem either. You don't need anything else.

[attie]

Awesome!

Thanks for taking another look :-)

[AndyC_772]

What do you mean by 'transient voltage suppressors'? Is it similar to a snubber (RC to GND)? That is something that I'm considering adding.

I mean a transient voltage suppressor diode - google "TVS diode" for info. They're like Zener diodes, but instead of being designed to have a very flat voltage characteristic in the reverse direction, they're made to break down very quickly and to be able to handle very large surge currents without damage. They're often used in parallel with devices that have a limited voltage rating and which might be damaged by inductive spikes and other noise - like a MOSFET, for example.

Do you have any advice for component power ratings?

How long is a piece of string? Work out the actual power you'd expect to be dissipated in each component, given the load it's driving, then add whatever you believe to be a sensible margin. Consider worst case fault currents rather than normal operating conditions too, you don't want something that works fine until the motor stalls, then catches fire.

IMHO if you're making a small quantity of something, then big, higher rated components are the way to go. The extra cost is minimal compared to the hassle of a repair or redesign.

With regard to keeping the current circulating, I was going to activate the low-side FET of the hi coil when PWM is low (if that makes sense). Are the body diodes not enough? And with regard to the FETs, I'm using all N-channel, so hopefully that clears up your confusion.

I guess they might be OK - just wanted to flag it up as something to check. Don't rely on being able to turn a FET on instantly, it takes time to charge the gate.

[lgbeno]

Cool project, I'm doing one similar using msp430.  Which micro are you using?  Also just checking to be sure how you implemented you NMOS gate drives, especially on the high side fets.

[Kremmen]

One comment, or maybe more an observation: IR half bridge drivers have been specified in the schema. If you look at IR datasheets you will notice that they always draw the circuit in a specific pattern, with voltages Vs, Vb directly opposite the bridge FETs. That is how it should be also in practice - that you minimize the length of tracks connecting to the bridge itself, and the power switches. In this schema the wires meander to the other side of the symbol, and it is a mindset that must not be reflected in the actual PCB.

The attached PCBs seem to be nicely laid out so there is no problem with this. Like i said, just an observation.

[Niklas]

I am a bit concerned about the placement of decoupling and boost capacitors on the MOSFET drivers. Taking U1, C2, C22 and D2 as an example, there is a long distance between C22 and pin 1 on U1. I think I would have placed the components like this:
- Swap places of C2 and R3
- Put C22 vertical to the left of U1, GND up
- Put D2 to the left of where R3 is now, cathode to the right
- Try to move the via hanging from pin 8 on U1 up a little bit to get the splitted GND plane to rejoin. C22's connection to pin 7 on U1 should be short and wide

If the polygon pour is unwilling to join with pins or with itself at the corners of the QFP-packages, then add a wire manually,  change its net name to GND and then repour. I remember having some problems with this on EAGLE 4.16 a couple of years ago.

[attie]

Thanks for your extra replies! I'm not sure how I missed them...

I am a bit concerned about the placement of decoupling and boost capacitors on the MOSFET drivers.

Eep! good spot, thanks.
I'm adding an LVDS chip to the UART of the AVR for off-board communications. That prompts/requires a bit of a re-design, so I'll be sure to move C22 and friends.