High current traces meeting small component legs

[Infraviolet]

P.S. throughout this post, I'm only considering two layer boards with both sides exposed to air (exposed copper or copper under soldermask), no need to worry about internal layers...

When one is designing high current traces the rule is to keep them as wide as possible, and pepper them with untented vias so as to provide extra surface area exposed to the air through which heat can escape.

But one often finds there are chips designed for high current applications on which the pins are pretty small.

For a trace carrying 15 amps in typical thickness 30um copper, if 15 celsius of warming is acceptable one needs a width around 11.5mm. 

But looking at the sort of chips one might be using with currents of this level, say an IFX007 or BTN7960 half bridge, a pin itself is only 0.6mm wide, with a recommended pad footprint of 0.8mm * 4.6 mm. If one is running from a solder pad this small to another component, say a high power rated shunt resistor only a few mm away, then what is one to do?

Does it actualy help to have a wide trace in circumstances where the width is much greater than the length? Or is this a matter less of providing a wide trace to decrease resistance, than of having a copper path to a nearby big area of copper to act as a heat dumping region? In which case does one simply provide acopepr path, even a relatively narrow one, from the short section of narrow trace where heat is generated, to some big region full of thermal vias and with large copper planes on both sides of a board.

Those half-bridge chip are rated for up to 50 amps continuous, how on earth can one hope to get traces wide enough for that to come anywhere near to the chips? How can chip designers rate chips for huge currents when the pins themselves are small enough and close enough together to make accessing them with sufficiently wide traces impossible.

Also the question of thermal reliefs comes up. For normal circuit components with low currents, one puts narrow bars of copper between solder pads and ground planes, so when soldering the heat from the iron (or reflow oven) doesn't escape to large ground (or other) planes too easily to let the pad be brought up to soldering temperature.

From a current handling perspective thermal reliefs are obviously not optimal, but are they sufficiently bad one should avoid them entirely when high currents are involved and therefore face difficulty when soldering. Or is it usual for one to still include them, afterall the pad may be small anyway, and trust in any nearby large planes of copper to dissipate heat despitethe increased thermal resistance from pin to plane that the thermal relief pattern produces? If one doesn't include them, then unless a particularly powerful iron is used there would be a plausible risk of boards being impossible to solder to, such would be the thermal mass immediately attached to particular pads?

The twin needs of keeping heat concentrated when soldering but letting it spread out when running a high current during board operation are clearly in conflict, what is the usual solution? Is there one possible without complex thermal modelling of a system?

Considering the half-bridge situation again, those example chips have big pads on the output pin for dumping the heat generated inside the chip, but in any high current application there will also be high currents at the ground and supply pins of such a chip. If one is using the chip in a buck-converter like manner then, when time averaged, only the output and ground pins experience high currents, the supply pin wouldn't when time averaged, but that is still more than just the output pin.

With a chip like this then, what does one do about keeping the ground and supply pins cool? Any heat generated in the chip will be dumped out through the big output pad area, but the heat generated within the supply and ground pins themselves, and within the solder joint between the pins and the section of narrow trace immediately connected to those pins, before there is any space for the trace to be widened out, will concentrate at those pins. If a large current is flowing then the heat arising in the pins alone, quite apart from the heat generated within the chip, becomes a thermal nightmare of its own.

How is this sort of thing typically handled?
Thanks

[thm_w]

Good idea to look at the manufacturers dev boards and see what they've done: https://www.infineon.com/cms/en/product/evaluation-boards/bldc-shield_ifx007t/

If its only a few mm's away then the power loss will likely not be significant. But you can use a trace calculator to figure it out, and determine if thicker copper might be needed.

[Shell Albert]

As you know, if a IC was released on market, then it was proved to have ability to hold its rated current described in its datasheet. so don't worry about anymore,  on PCBs, an old engineer in my company suggested us to draw a big copper shape under the pin, for high current circumstances, doing the calculation is better, but for normally, we just draw a big sufficient shape because we have more space on PCBs.

[T3sl4co1l]

Ampacity only applies when the trace/wire is long enough that heat flow is entirely lateral, through insulation, into convection, etc.

For short wires and traces, heat flows along the length, and the bits at either end serve as heatsinking.

SMT packaging isn't especially conductive, but it's better than air, so heat spreads out within the package, and moreso where metal parts are present: leadframe, heatsink, etc.  Indeed, the wirebonds within the package are even tinier, and they handle amperes just fine. (Well, maybe not amperes each, but they might use a few in parallel, or thicker ones too.)

If you don't mind the voltage drop, and the heat can be dissipated effectively, there's essentially no limit to the current density you can put through a metal.  Signal size PCB traces can handle dozens of amperes for a brief time, hundreds even, before physical effects start to take over (at short enough time scales, skin effect takes over and cross-section can reduce significantly, and dI/dt * stray inductance can dominate to the point it arcs over instead; whatever the mechanism, see "exploding bridgewire").

As for pours, and especially when width exceeds length, ampacity rules completely go out the window.  Current itself isn't even spreading out evenly through such a conductor, and current density is concentrated near the pins, and in the region between them.  You could trim away all the material outside that current-carrying region, and get about the same total resistance, but ampacity would go down because the excess is still providing heat dissipation.

Better still: butt the components right next to each other, minimizing path length through PCB foil.  The best watt saved is the watt never dissipated.  If you can't arrange everything quite this close, consider adding current/heat spreaders to the design -- you can SMT chips of copper or brass, for example,

Tim

[Doctorandus_P]

Also, the pins of such IC's may be narrow, but they are also much thicker then the 35um of a "regular" PCB. High current PCB's often also have thicker copper.  And it also helps to have wide copper close to the pin. It helps as a heatsink, and this is commonly also used for power electronics that dissipate power (Linear voltage regulators, class A/B amplifiers, etc).

[Infraviolet]

Thanks for the extra details. All the online calculators I've found use a model where the trace in which the current flows is the only copper, and it isn't connected to bigger pours for heat dumping, so are there any rules of thumb or empirical equations to approximate (to the nearest 10 celsius maybe) how much temperature rise you get when you have a short, narrow high current trace where the current actually flows but connected by copper to a much bigger pour (or even a pour on both sides with lots of unfilled thermal vias to increase the surface area contacting the air) some distance away.

[T3sl4co1l]

Nope!  Get out the thermal simulator, or the IRL equivalent (build and test it).

On the upside, the lateral heat spreading ability of, say, 2oz x 2 layer FR-4 is about an inch or two, so, anything within that area (if it's not stupendously intense) will tend to spread heat out into that area (i.e. a circle a couple inches across), and the power dissipated in those local areas merely contributes to overall temp rise, with a modest local rise depending on how well heat is sunk away from the heat-generating area in the first place.

You can do basic approximations of, what if we have this much current in this rectangular segment of copper, which makes this power, which flows through that segment, and etc. etc.  Neither heat nor current flow in uniform directions, so the value of such approximations is quite limited, but you can still hand-wave a basic guess like to say the local area isn't going to be more than x°C above the nearby area, and that the nearby area is ballpark y°C higher due to that current flow, etc..

Tim

[mag_therm]

After also pondering about this subject on (already built)  RF linear amp using T0267, last night I added the drain lead and pcb track to the 2D heatsink model.
Quickfield 2D model was adjusted as follows:
The 100mm long original heatsink model was shortened to a slice exactly 3mm long (into page) to match the drain leg width .
The  addedd pcb substrate is  1.6mm thick. Track is  1 Ounce ( 0.35mm thick)

The DC conduction model was coupled to provide track heating. Due to dimensions of the pcb track and the MosFet drain leadout, this should be accurate enough up to about 3 MHz.
It became apparent the the DC current flowing in the 3mm wide pcb track would need to be increased above the actual drain current, in order to visualize  track heating contribution.  So DC current along track into drain is 11 Amp. Also the track was lengthened to enable visualization of the temperature along the track, away from the TO267.
All surfaces in the model are cooled by Convection: 20 W/m^2.K, Radiation E=0.5, to 30C

Not knowing the thermal resistance from Silicon to the drain lead, I solidly joined them.
The silicon heat generated in the TO267 is sufficient to cause the heatsink temperature to be 47C. That is heatsink operating temp in the cabinet which has ambient of about 30C. The case temperature is then 60C which is near to thermocouple measurement.

Here is a section of the transient thermal results at T=2400 second:
https://app.box.com/s/wvhkshkswyijiiy7v3h8c4ra6fn59m70
Here is a close-up of the power loss in the track and the soldered drain leadout due to the 10Amp DC only
https://app.box.com/s/6f6bb2d5fdzjs8bwipz8gxpxotgqvr3c

Conclusion for this model: The junction heat generated in the TO267 is swamping the heating of 10 Amp flowing in the 3 by 0.035 mm pcb track.
Note the direction of the heat flux arrows.

If there is any data for the typical thermal resistance between drain pin and junction, I could re-run model using that.