High-Speed PCB EDA and simulation recommendation

[mmartc_]

Hello everyone,

I'm starting a new challenge in high-speed PCB design for fibre optics systems. I will be dealing with several SerDes channels running at 28Gbauds and rise-times of 10ps. I found the books by Dr Howard Johnson and Lee W. Ritchey and I'm reading them already.

At the same time, I'm exploring the possibility to update our EDA tool, which is quite old and doesn't include any simulation capabilities.

I am a former Altium Designer user and I really like the tool. The design flow is smooth and the GUI is very intuitive. But I'm not sure if it covers our present and future needs in SI simulation. So I started a demo of PADS Professional (based on Xpedition), which has HyperLynx included. PADS Professional looks really old, pretty much un-updated for a really long time. The GUI is not intuitive and the whole design flow feels kind of fragmented in several applications developed by different teams. Sometimes I end up wasting a lot of time trying to figure out how to solve problems with the tool. Also, I don't find the documentation very good, it's difficult to find information on the internet and the library management feels heavy and really time-consuming.

 I would like to know what are your experiences with other EDA tools for High-Speed. What do you use for this kind of design?

[nctnico]

I'm using Orcad PCB Designer professional (from Cadence)  for high speed circuits. The crosstalk and impedance simulation doesn't need anything to setup besides the board stackup and Er numbers for the dielectrics. Recently I imported a design made in Altium in order to do these checks as these simulations seem to be hard to do with Altium.

[mmartc_]

I'm using Orcad PCB Designer professional (from Cadence)  for high speed circuits. The crosstalk and impedance simulation doesn't need anything to setup besides the board stackup and Er numbers for the dielectrics. Recently I imported a design made in Altium in order to do these checks as these simulations seem to be hard to do with Altium.

Great! I already requested the trial. I guess this is the cheap alternative from Cadence in contrast to Allegro right?

[nctnico]

PCB Designer is Allegro (Cadence is horrible at product naming). Depending on the license features get enabled / disabled. For high speed work you need at least PCB Designer professional.

[mmartc_]

I'm also considering going for Altium + HyperLynx. In theory, you can import any design in ODB++ format into HyperLynx.

[nctnico]

One thing to consider is the amount of effort to setup simulations. If the process is too tedious, it might be too much effort.

A field solver like Sonnet (there is a free lite version) can also be used to simulate PCB stackups and traces in great detail.

[jahonen]

I have been playing with HyperLynx for a while and I can say that you definitely need also full wave solver option to fully simulate transition regions (e.g. vias and component pads) at those speeds. I also have used Ansys SIwave / electronics desktop, but I think that is more oriented to frequency domain problems although it can also solve time domain things. SIwave workflow is much slower, though.

HyperLynx FWS integrates very nicely to the workflow and really only extra thing you'll need to do is to create 3D areas (which HyperLynx creates pretty much automatically) and then solve those areas.

Also, there are some problems with the ODB++ file produced by Altium Designer which may or may not affect your simulation workflow, like that for some reason ODB++ component pin names seem to include the reference designator prefix added to them which prevents one using IBIS models unless you edit the ODB++ file using text editor and repackage the thing (say, pin A1 of component U1 becomes for whatever reason U1-A1 in AD ODB++ export!). This bug was confirmed by Altium and is in the works, but no idea if/when that will be fixed.

For me, this was a complete killer when using DDRx wizard to verify DDR4 routing in HyperLynx, since that relies heavily on the IBIS models and pin names need to be correct.

Regards,
Janne

[mmartc_]

One thing to consider is the amount of effort to setup simulations. If the process is too tedious, it might be too much effort.

A field solver like Sonnet (there is a free lite version) can also be used to simulate PCB stackups and traces in great detail.

Yes, well noted. I have both demos available at the moment, I'd better test how good is the interaction between tools hands-on.

I have been playing with HyperLynx for a while and I can say that you definitely need also full wave solver option to fully simulate transition regions (e.g. vias and component pads) at those speeds. I also have used Ansys SIwave / electronics desktop, but I think that is more oriented to frequency domain problems although it can also solve time domain things. SIwave workflow is much slower, though.

HyperLynx FWS integrates very nicely to the workflow and really only extra thing you'll need to do is to create 3D areas (which HyperLynx creates pretty much automatically) and then solve those areas.

Also, there are some problems with the ODB++ file produced by Altium Designer which may or may not affect your simulation workflow, like that for some reason ODB++ component pin names seem to include the reference designator prefix added to them which prevents one using IBIS models unless you edit the ODB++ file using text editor and repackage the thing (say, pin A1 of component U1 becomes for whatever reason U1-A1 in AD ODB++ export!). This bug was confirmed by Altium and is in the works, but no idea if/when that will be fixed.

For me, this was a complete killer when using DDRx wizard to verify DDR4 routing in HyperLynx, since that relies heavily on the IBIS models and pin names need to be correct.

Regards,
Janne

From what I read on the HyperLynx website, there is an option tailored for SerDes channel design, which includes a full-wave solver and checks the conformity to several protocols we use in our designs:

https://eda.sw.siemens.com/en-US/pcb/hyperlynx/signal-integrity/serdes-channel-design-hyperlynx/

I guess it's going to be extra expensive.

Regarding the bug, I've found an old post in the Siemens forum:

https://community.sw.siemens.com/s/question/0D54O00006eo6PqSAI/what-is-the-best-method-for-working-with-an-altium-to-hyperlynx-setup

[jahonen]

I see, it looks like that has been around for a while. I guess there is no hope of having a quick fix, so better keep the text editor around

Yes, SI tools are quite expensive. HyperLynx FWS is not however terribly expensive compared to the software itself.

Mentor/Siemens has also rental licenses, have you considered that? We were planning of getting perpetual license of HyperLynx for our company but it turned out to be simply too expensive.

So we have been getting 1 month rental licenses (you can also get longer ones, like 6 months or so and 6 months may be cheaper per time unit), which basically works ok. Only bad thing is the hassle of changing/updating license files once in a while.

Regards,
Janne

[mmartc_]

That might be a good option as well. I will ask for the prices of perpetual and rental licenses.

There's a company called Sintecs that develops a connector to integrate HyperLynx in the Altium workflow:

https://sintecs.eu/eda/hyperlynx-connector/

Although I think it's intended for HyperLynx SI ALT and not the GHz bundle.

[nctnico]

BTW: one of the things to keep in mind is that the glass weave pattern is also going to play a big role at high (several GHz) frequencies. Be sure that you factor this in either through simulation or just by understanding what is going on. From what I've read is that the trick is to make sure that both signals from a pair are affected equally in order to maintain a balanced signal.

[jayk]

PADS Pro is difficult to learn, and the documentation is pretty bad.  One trick, if you have a maintenance contract, is to put in a support request for something you're stuck on.  Most of the time an support engineer will contact you within a day and you can generally get them on a webex to help figure out what's going on and this is a good opportunity to ask any other questions you have.  I haven't used Altium or Cadence products for several years, but I don't remember it being easy or even possible to do a webex with a support engineer.

They also have some decent on-demand training - you run through some lab exercises on a pre-configured AWS instance.  I'm not sure if this is available for evaluation versions of the product, but I think it's included if you have a license for PADS Pro.

The version of Hyperlynx included with PADS Pro won't simulate vias at all.  I think the lower-end 'stand-alone' versions have analytical via models good up to several gigahertz and above that they recommend using their full-wave solver to generate s-parameter models of the vias.  Like someone said this is pretty well automated within the tool.  The DDR wizard is a pain to set up, but it seems very comprehensive and can catch some really subtle layout mistakes.  I've never looked into pricing on Hyperlynx, but I suspect it gets pretty expensive.  The rental option sounds like a good way to go, or maybe finding someone with a license and hiring them to run your sims.

Intel/Altera has published some really good app notes that tell you most of what you need to know for high-speed routing... see AN-672.  They did a bunch of sims on various anti-pads sizes, via clearances, etc., and just following their guidelines may be enough to get you a working board, even at 28G.

[Feynman]

Yeah, we also had a look into PADS Prof. And also considered the user interface not very intuitive.
I would recommend a PCB tool that suits you well and has the possibility to export to HyperLynx, That would be anything that exports to ODB++. Maybe HyperLynx can import neutral formats like IPC-2581 or Gerber, not sure. Since it is ex-Mentor maybe ODB++ is the only real transfer option.

[PlainName]

I haven't used Altium or Cadence products for several years, but I don't remember it being easy or even possible to do a webex with a support engineer.

I've done that (Altium web chatting thing). Typically in the middle of the night UK time and been connected to an Australian support person pretty much instantly. Once I had an issue that prevented generation of some output that I had to send off within an hour, and the UK support set up a Zoom-alike session to figure out the issue and walk me through the resolution.

Against that, I raised a bug issue and that took several back-and-forths over a week or so to get them to recognise the problem. But overall Altium support (if you have maintenance) has been in the 4/5 star class for me.

[jahonen]

That weave effect is important consideration for high speed differential pairs. One way to deal with that is to request the PCB manufacturer to rotate the manufacturing image on the panel so that traces do not align with the weave pattern, like 22.5 degrees of rotation for usual 45 degree bends.

The main difficulty is that you really can't control how traces will align themselves onto the weave pattern, thus it is not practical to try to simulate what will happen, or maybe the worst skew scenario if you know the Dk difference between epoxy and glass fibers. In worst case, the other differential pair signal is on top of the glass fiber and other is on top of the epoxy. That will introduce skew to the differential pair signals and degrade the signal.

Regards,
Janne

[mmartc_]

BTW: one of the things to keep in mind is that the glass weave pattern is also going to play a big role at high (several GHz) frequencies. Be sure that you factor this in either through simulation or just by understanding what is going on. From what I've read is that the trick is to make sure that both signals from a pair are affected equally in order to maintain a balanced signal.

I wasn't aware of the weave pattern until you mentioned it. The application note suggested by jayk also covers this issue:

https://www.intel.com/content/www/us/en/docs/programmable/683624/current/fiberglass-weave.html.

Thank you very much for pointing out that AN, it's great.

PADS Pro is difficult to learn, and the documentation is pretty bad.  One trick, if you have a maintenance contract, is to put in a support request for something you're stuck on.  Most of the time an support engineer will contact you within a day and you can generally get them on a webex to help figure out what's going on and this is a good opportunity to ask any other questions you have.  I haven't used Altium or Cadence products for several years, but I don't remember it being easy or even possible to do a webex with a support engineer.

They also have some decent on-demand training - you run through some lab exercises on a pre-configured AWS instance.  I'm not sure if this is available for evaluation versions of the product, but I think it's included if you have a license for PADS Pro.

The version of Hyperlynx included with PADS Pro won't simulate vias at all.  I think the lower-end 'stand-alone' versions have analytical via models good up to several gigahertz and above that they recommend using their full-wave solver to generate s-parameter models of the vias.  Like someone said this is pretty well automated within the tool.  The DDR wizard is a pain to set up, but it seems very comprehensive and can catch some really subtle layout mistakes.  I've never looked into pricing on Hyperlynx, but I suspect it gets pretty expensive.  The rental option sounds like a good way to go, or maybe finding someone with a license and hiring them to run your sims.

Intel/Altera has published some really good app notes that tell you most of what you need to know for high-speed routing... see AN-672.  They did a bunch of sims on various anti-pads sizes, via clearances, etc., and just following their guidelines may be enough to get you a working board, even at 28G.

Well, I guess that means that the HyperLynx included in PADS professional is not so different from the SI tool included in Altium, which is able to use IBIS models and simulate what happens in the transmission lines when you drive them with rising and falling edges.

That weave effect is important consideration for high speed differential pairs. One way to deal with that is to request the PCB manufacturer to rotate the manufacturing image on the panel so that traces do not align with the weave pattern, like 22.5 degrees of rotation for usual 45 degree bends.

The main difficulty is that you really can't control how traces will align themselves onto the weave pattern, thus it is not practical to try to simulate what will happen, or maybe the worst skew scenario if you know the Dk difference between epoxy and glass fibers. In worst case, the other differential pair signal is on top of the glass fiber and other is on top of the epoxy. That will introduce skew to the differential pair signals and degrade the signal.

Regards,
Janne

Will check with our manufacturer about that possibility.

At the moment I feel more confident with the Altium + HyperLynx option for the budget we have. I really know how to use the tool and that will speed up the design process. I don't find any lack of features in Altium to discard the tool. It can handle the controlled impedance traces, the length match between pairs and within pairs, and different vias configurations to get rid of the stubs.