High speed signal routing layers

[joniengr081]

Referring to section 3.2 High Speed Differential Signal Rules. Page 9/21 of the attached document "High-Speed Interface Layout Guidelines" – NOVEMBER 2018 – REVISED FEBRUARY 2023

Point number 4: "When possible, route high-speed differential pair signals on the top or bottom layer of the PCB with an adjacent GND layer. TI does not recommend stripline routing of the high-speed differential signals."

Given microstrip is not symmetric compared to stripline having reference layers on top and bottom. If differential signals, there are two components, one is common signal or the common voltage level and the other is differential signal or the differential voltage level. I guess in the asymmetric geometry the speed of the common part and the differential part does not remain the same as in case of microstrip and that is the reason we do not route high speed signals on top and bottom layers. Because of symmetric geometry in case stripline, we route the high speed signals in inner layers.

But the TI document is describing something which is opposite.

[Uky]

I agree. TI makes a strange statement. What I myself have been practicing is to get down to inner layers as soon
as a differential pair exits an IC. The Top layer being GND, the next layer Signal and then another GND.

Or if it is really high signals in order to avoid back drilling - I use the next to bottom layer for the differential signals
and keep a tight control of via structure impedances. Lots of GND-stitching vias ...

The thing to remember is that the trace widths for Z and the propagation delay (most likely!) differs between routes
on TOP vs inner layers. This has to be either set up in a constraint manager or the CAD engineer has to make the necessary
calculation himself (or herself)

My own experiences of using inner layers has been that it was possible to acheive adequate performance for 10GBit+
differential signals in communication systems.

 

[joniengr081]

Yes, exactly. I agree with Uky.

We actually are working and designing board having signals up to 10 Gbps and we were considering inner layers for routing high speed signals but after reading the TI document we need to re-consider.

[Feynman]

TI's recommendation doesn't make much sense to me, either.

You are correct in that the different modes travel with different velocities on outer layers. That's because the respective fields "see" a different effective dielectric constant. For the same reason, there is (in theory) no far-end-cross-talk when two traces are surrounded by a homogeneous dielectric material like in a stripline topology.

Of course, it all depends on the specific application, but - generally speaking - high-speed signals are preferred to be stripline instead if microstrip.

[joniengr081]

This is exactly written in the book “Signal Integrity and Power Integrity – Simplified” written by Eric Bogatin.

The following text is taken from Chapter 11: Differential Pairs and Differential Impedance

Even and Odd Modes

There are two special voltage patterns we can launch into the pair that will propagate down the line undistorted.

The first pattern is when exactly the same signal is applied to either line; for example, the voltage transitions from 0 v to 1 v in each line.

The second special voltage pattern that will propagate unchanged down the differential pair is when the opposite-transitioning signals are applied to each line; for example, one of the signals transitions from 0 v to 1 v and the other goes from 0 v to –1 v.

To distinguish these two states, we call the state where the same voltage drives each line the even mode and the state where the opposite-going voltages drive each line the odd mode.

Velocity of Each Mode and Far-End Cross Talk

The description of the signal in terms of its components propagating in each of the two modes is especially important in edge-coupled microstrip because signals in each mode travel at different speeds.

The velocity of a signal propagating down a transmission line is determined by the effective dielectric constant of the material the fields see. The higher the effective dielectric constant, the slower the speed, and the longer the time delay of a signal propagating in that mode.

In the case of a stripline, the dielectric material is uniform all around the conductors and the fields always see an effective dielectric constant equal to the bulk value, independent of the voltage pattern.

The odd and even-mode velocities in a stripline are the same.

However, in a microstrip, the electric fields see a mixture of dielectric constants, part in the bulk material and part in the air. The precise pattern of the field distribution and how it overlaps the dielectric material will influence the value of the resulting effective dielectric constant and the actual speed of the signal. In the odd mode, more of the field lines are in air; in the even mode, more of the field lines are in the bulk material. For this reason, the odd-mode signals will have a slightly lower effective dielectric constant and will travel at a faster speed than do the even mode signals.

In a stripline, the fields see just the bulk dielectric constant for each mode. There is no difference in speed between the modes for any homogeneous dielectric interconnect.

In an edge-coupled microstrip, a differential signal will drive the odd mode so it will travel faster than a common signal, which drives the even mode.

[joniengr081]

Any further discussion ? Should we route high speed differential signals in inner layers or outer layers ?

[free_electron]

outer.
why ? because of the materials
an embedded stripline is always constructed with a core on one side and prepreg on the other side. the thickness of the prepreg is "fluid". so you can make the distance from signal to ground hard ( core)  where the distance to the next layer will be a prepreg that is pressed out.
second problem : weave discontinuity. now you have to deal with glass bumps ( assuming you don't use paste materials nelco or rogers. ).

when the trace is at the surface you can design the board so that it is a core stack. now you only have to deal with one weave ( in the core) and air. strip the soldermask because that is also a problem area . the dk of soldermask can wildly fluctuate.

it's all about removing unknowns.

[nctnico]

In the end you'll also need to take into account the tolerances of the drivers and receivers. IIRC the tolerance is at least 10% (45 Ohm to 55 Ohm). Don't be surprised it is 20% in some cases. Besides tolerances from weave and stackup, you'll also have etching tolerances. On very thin traces (close to the minimum width of the etching process), this can easely be 20% as well.

When dealing with differential pairs, the tolerance on matching the phase between the members of the pair is more important than getting the exact impedance.