that's not how it works.
4 layers start off as a double sided board.
0 ) take double sided board , apply dry-film photoresists , expose (mask or LDI or maskless imager) , develop.
1 ) etch the copper structures ( we don't drill holes ! )
2 ) apply isolation material ( prepreg ) on the outsides , then cover in copper foil and bake it in a press.
3) drill all holes that need plating
4 ) apply photomask (negative image ! copper that needs to remain is visible) , expose ,develop
5) plating. this is called selective plating. you only grow copper where needed (where the photo mask is open , and in the holes
6) tinflash. a layer of chemical tin is applied. the tin only sticks to the visible copper (traces and in the holes )
7) remove photomask
etch. only copper that is visible is eaten. the tin coated copper is not etched. the etchant only eats copper, not tin.
9) strip tin (if needed )
there are other processes like non selective plating where they plate before photomask. but that is wasteful: you grow copper to eat it afterwards. so it is not really done anymore
they always use negative mask. for reworkability reasons.
- negative mask HARDENS in light , positive mask weakens in light. so a negative mask only gets better (harder) when exposed to ambient light.
- negative mask remains can easily be removed (retouched). assume there is a speck of dust on the film. that area did not get light so the mask is not hard. after developing you see pinpricks (very easily spotted in the AOI as copper is refelctive. it lights up like a christmas tree ! . simply fill them with some resin and cure. Worst case you will have a tiny little hole in the copper. with positive mask a speck of dust becomes copper ! risk of shorts !
opens are easier to find during electrical test. you only need to test end-to-end on a single node. a sort is hard. you need to test any trace against any other adjacent trace.
there are many more steps that i have skipped. planarisation, backbuttering ,copper rough-up wall activation before plating. post plating ENIG , ENEPIG , HASL. soldermask , designator
you want to reduce runtime.
a six layer is different.
you can do a core and have two laminations. but that means two times in the oven. that makes the board brittle and takes a lot of time ( 4 to 6 hours per run)
so the best is to make two double sided etched boards , put some insulation between them , apply oute foil , dril , mask , plate ,tinflash, etch
you only have to do the oven step once.
with 8 or more layers all bets are off. you can do 3 cores (6 layers) and do a single oven run. but when you start playing with blind and buried vias or layer vias the whole thing goes out the window.
most costly is ELIC (every layer interconnect). that uses laserd, stacked vias and requires an oven run per layer you add. but it is extremely flexible as you can make exactly what you need. gor from layer 2 to layer 9 ? no problem. 2 to 8 , 2 to 7 3 to 6. anything goes. you are not bound by symmetry or pairs. you also have no stubs
things get even more complicated as you start doing via in pad or backdrilling and plugging. there are interconnections between layer 2 and four but they are not visible on the outside. they have been selectively drilled and capped by the outer foil. that can be done for signal integrity , but also for creepage reasons. high voltage boards do not want access to the internal nodes , or even have the ability for copper to zap through. those are special techniques and you CAD software needs to support that. it requires specials rule sets. and the tool needs to understand that process.
and we have not touche resistive or capacitve embedded layers or even embedded components , where elements are actually buried inside the board.
and then there is flexible board, rigid-flex, metal core , embedded wires and copper coins (for thermal or current reasons) . boards with thick copper inside and thin outside.
3D printed boards (FDM)
There is a lot of technology in a pcb.