I've seen some video tutorials and read some info but seens like no body pay much attention about accuracy while drawing the silkscreen... I mean... the tutorials mention that silk screen must be drawn on its respective layer but they don't mention anything about taking into account the trace width used to draw the package outline...
I wish I could explain better but can find the words so i attached two images:
- In one image I didn't take into account the trace/line width so the component will overlap the silkscreen when placed on the board (silkscreen2.png)
- I the other image I took into account the trace width so the component will not overlap the silkscreen so it can be used to accurately align the component while manually placing the components on the board (for automatic component placement we need fiducials, right?) (silkscreen1.png)
Anyway, I'm probably asking a non sense since components are not manufactured perfectly and the final measurements of the package outline will vary according to the tolerances of the manufacturer... also probably the silkscreen tolerances and accuracy will vary from one pcb manufacturer to another, also some components will align themselves due to surface tension but... Do you think is worthy to accuratelly define the package outline as I show in the "silkscreen1.png" image?
EDIT: Forgot to mention that I was asking if is worthy to accurately draw the package outline in the silkscreen(tplace) and tdocu for SMD packages like QFN, BGA, etc... obviously TH packages will align itself according to their pins