I have a TO-220 package I am going to mount horizontally on my board, and I plan to solder the tab to an exposed copper area on the ground plane. I also have a bunch of vias for heat transfer to the bottom ground plane.
Trouble is, I don't know how much area to allow around the tab for good soldering. At the moment I have 0.025" margin. Not enough?

The datasheet for my particular IC doesn't indicate that the tab on the package has chamfered corners or concave cut-outs on either side, so I can't rely on that for extra room for solder.
Also, if I increase the area, I have room for another line of vias around the top and sides. More is better, right? Or would there be negligible effectiveness for anything not right under the tab?
By the way, I couldn't figure out in DipTrace (if it's even possible) how to mask out an area of silk screen. At the moment, as can be seen, the silk outline for the TO-220 is over the exposed copper. From my research here, I
think that virtually all PCB manufacturers will trim the silk screen layer according to pads, exposed copper, etc. and that part won't be printed on final boards. Is it safe to rely on this, or should I edit my component pattern/footprint to remove the overlapping lines?