Electronics > PCB/EDA/CAD
How to Use Vishay's MOSFET models in LTSPICE
palpurul:
Hello,
I am trying to simulate a MOSFET(SISS10ADN) that I picked from Vishay. I'd like to incorporate them into my design , but I want to simulate them first in LTSPICE. Vishay gives me a bunch of models (I think) that can't really simulate in LTSPICE.
When I try to run it, LTSPICE gives me this:
Error on line 13 : r:u1:1 +12v«:d» u1:3 1.700e-03 3.725e-03 1.827e-05
Unknown parameter "1.827e-05"
Error on line 17 : r:u1:tcv u1:100 n001«:s» 1e6 1.266e-04 1.174e-06
Unknown parameter "1.174e-06"
Error on line 24 : .model u1:dbd d ( fc = 0.1 tt = 3.088e-08 tref = 25 bv = 41 rs = 1.115e-02 n = 9.388e-01 is = 1.078e-13 eg = 1.495e+00 xti = -9.765e+00 trs = 3.626e-03 cjo = 2.702e-10 vj = 8.119e+00 m = 1.000e+00 )
* Unrecognized parameter "trs" -- ignored
Error on line 23 : .model u1:pmos pmos ( level = 3 tox = 5e-8 nsub = 3.967e+16 is = 0 tpg = -1 capop = 12 )
* Unrecognized parameter "capop" -- ignored
Error on line 22 : .model u1:nmos nmos ( level = 3 tox = 5e-8 rs = 0 kp = 9.844e-06 nsub = 5.390e+16 kappa = 1.073e-01 nfs = 1.009e+11 ld = 0 is = 0 tpg = 1 capop = 12 )
* Unrecognized parameter "capop" -- ignored
WARNING: Node N004 is floating.
WARNING: Node N003 is floating.
WARNING: Less than two connections to node N004. This node is used by C1.
WARNING: Less than two connections to node N003. This node is used by C1.
Instance "m:u1:2": Length shorter than recommended for a level 3 MOSFET.
Instance "m:u1:1": Length shorter than recommended for a level 3 MOSFET.
Direct Newton iteration for .op point succeeded.
Singular matrix: Check node n004
Iteration No. 1
Fatal Error: Singular matrix: check node n004
Iteration No. 1
This circuit has floating nodes.
I tried all of the models in the folder that I downloaded from Vishay's website, but they all give similar errors. Can they work in LTSPICE at all?
Link to MOSFET models: https://www.vishay.com/product?docid=79237&tab=designtools-ppg
T3sl4co1l:
Change the resistor second parameter from comma-separated to "TC2=".
PSPICE is weird.
Similarly, you'll have to find equivalent for the extra device parameters, or maybe it works okay without them.
Or no wait, HSPICE actually? Yeesh, a bit of an adventure to find what document I'm looking for. It's in here:
http://www2.ece.rochester.edu/courses/ECE222/hspice/hspice_mosfet.pdf
Doesn't sound very unusual, CAPOP = 12 "Ward Dutton model" something or other, which seems to be an old method (published in the 70s), would that not be a normal model integrated with plain-vanilla SPICE then? No idea.
And TRS is just a tempco for RS, if nothing else, the diode can set RS = 0 and then implement it separately (a resistor of R = RS and TC1 = TRS in series).
Tim
palpurul:
--- Quote from: T3sl4co1l on October 15, 2021, 09:26:36 pm ---Change the resistor second parameter from comma-separated to "TC2=".
PSPICE is weird.
Similarly, you'll have to find equivalent for the extra device parameters, or maybe it works okay without them.
Or no wait, HSPICE actually? Yeesh, a bit of an adventure to find what document I'm looking for. It's in here:
http://www2.ece.rochester.edu/courses/ECE222/hspice/hspice_mosfet.pdf
Doesn't sound very unusual, CAPOP = 12 "Ward Dutton model" something or other, which seems to be an old method (published in the 70s), would that not be a normal model integrated with plain-vanilla SPICE then? No idea.
And TRS is just a tempco for RS, if nothing else, the diode can set RS = 0 and then implement it separately (a resistor of R = RS and TC1 = TRS in series).
Tim
--- End quote ---
Thank you I just omitted that line and it worked.
Now I have to make this model work.
Model: https://www.diodes.com/part/view/DGD05473?BackID=8231#tab-details
I renamed the extenstion as .cir and when I try to run it in LTSpice it gives me this error:
Fatal Error: Undefined subcircuit: :
How to make this one work?
Thank you so much
T3sl4co1l:
Eeeeh yikes, all those switches... you're probably better off using an E source and/or logic gates to fake it. SPICE doesn't like lots of abrupt characteristics like switches.
Probably the syntactic thing LT is choking on is the nested SUBCKT. Move the gen_switch block to the bottom (below the outer .ENDS).
Dunno about those pinnames things either. And colons in the param list?
Tim
palpurul:
--- Quote from: T3sl4co1l on October 16, 2021, 08:11:42 am ---Eeeeh yikes, all those switches... you're probably better off using an E source and/or logic gates to fake it. SPICE doesn't like lots of abrupt characteristics like switches.
Probably the syntactic thing LT is choking on is the nested SUBCKT. Move the gen_switch block to the bottom (below the outer .ENDS).
Dunno about those pinnames things either. And colons in the param list?
Tim
--- End quote ---
Thank you so much for your response.
I am getting into switching converter design and I decided to simulate them first. I really don't know if I have to use generic switch models or vendor supplied models. Eventually I'd like to simulate the loop and get the frequency response to monitor stability. Obviously I can't get the frequency response with those models (or can I?).
Do you have suggestion about this? Should I use average models or vendor supplied models to simulate switching converter circuits (both transient and AC response).
Thanks again you helped me a lot.
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