Electronics > PCB/EDA/CAD

Importance of Transfer Vias

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kaevee:
Lot's of PCB design tutorials say we need to add transfer vias for uninterrupted reference plane.

On the other hand, I see many reference designs and PCB layouts suggested by manufacturers not using transfer vias in their designs.

How important are transfer vias? What are the implications of not having them?

Can we skimp on them if we are routing SPI and GPIO signals?

ataradov:


You can get away with a lot of stuff. The question is - why? Reasonable amount of vias is free and in any case there is no downside to having them at all.

kaevee:

--- Quote from: ataradov on September 20, 2023, 04:24:58 am ---You can get away with a lot of stuff. The question is - why? Reasonable amount of vias is free and in any case there is no downside to having them at all.

--- End quote ---
I am following the guidelines and adding the transfer vias when changing layers.

I was wondering, when laying out in very tight areas, if I can get way by skimping on them as minimum via size low cost PCB manufacturers is about 0.3mm/0.5mm.

The video in the link answered the questions in my mind. Thank you very much.

Doctorandus_P:
If you are using a 4 layer stackup with signal layers on both outside layers, and a GND and a Power layer on the 3 inner layers, then it helps to put decoupling capacitors between the power planes at location of the via's.

The distributed capacitance is an advantage of such a stackup, but I think it is considered a (moderately) bad layer stackup. From what I remember it's better to use two GND planes and route the power as fat low resistance tracks (With decoupling caps of course).

Something else I found remarkable is the difference between 1 and 6 stitching via's @15:20 The red (high current density) does not change much, but the lower stray currents (green) almost disappears and turns blue. So why does Robert Feranec say the difference is small?

kaevee:

--- Quote from: Doctorandus_P on September 20, 2023, 11:49:37 am ---If you are using a 4 layer stackup with signal layers on both outside layers, and a GND and a Power layer on the 3 inner layers, then it helps to put decoupling capacitors between the power planes at location of the via's.


--- End quote ---

In 4 layer stackup signal/ground/power/signal, can we route on layer 3 without transfer vias as there is no change in reference plane (layer 2)?

EspressIf hardware design guidelines suggest above stackup and asks us to route the SPI lines on layer 3, which is power layer.

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