Insertion loss budget on PCB - PCIe Gen 3

[joniengr081]

I found this article which deals with the insertion loss budget for PCIe. I am looking for the table in which the total channel insertion loss budget for PICe Gen 3 (8 GT/s) is 22 dB which is distributed as Root Package (3.5 dB), CEM Connector (1.7 dB), Add-in Card (6.5 dB), Remaining Budget for System Base Board (10.3 dB).

https://www.electronicdesign.com/technologies/communications/article/21267698/astera-labs-how-to-manage-the-pcie-50-channel-insertion-loss-budget

Remaining Budget for System Base Board (10.3 dB): Is that the budget for PCB design ? Does it means that the PCB traces should not have more then 10.3 dB insertion loss ?