Is this 16 MHz crystal layout OK?

[exscape]

-- UPDATED:

Bottom layer cutout highlighted:

(before the update)

16 MHz crystal, 22 pF load capacitors, Atmega328 microcontroller... and a 100 nF decoupling cap. (I'm not a fan of the pin placement there.)

There's quite a bit of conflicting info about what's best. Some say you "must" have a ground plane, others say you shouldn't (mostly due to stray capacitance?). Some say you should have a ground ring on the top layer, while some seem to recommend a local ground plane... Needless to say, this is pretty confusing as I'm still pretty new to this.

The main requirement is that it works, really. Low EMI and noise coupling etc. is of course preferred, but isn't as critical as having it work.

EDIT: I just realized that the crystal cap ground current will pass through the same trace as the main power will, at least in part. Should I remove that connection (between the right pad of C11 and the left pad of C8)? -- I did so and updated the post above.

[Short Circuit]

...
There's quite a bit of conflicting info about what's best. Some say you "must" have a ground plane, others say you shouldn't (mostly due to stray capacitance?). Some say you should have a ground ring on the top layer, while some seem to recommend a local ground plane... Needless to say, this is pretty confusing as I'm still pretty new to this.

It doesn't matter that much since all these claims are backed by working designs.
In fact, I think it would be quite difficult to screw the oscillator by layout mistake alone.

[jimmc]

C11, C12 and the crystal (which is inductive at the frequency of oscillation) form a tuned circuit. For minimum radiation or pickup, ensure that the area enclosed by currents circulating in this loop is minimised.
To do this place C11 & 12 alongside the crystal with their earthed ends close together in the middle.
Personally I would use an earth plane unless it's a multi-layer board with a very thin (0.005") dielectric under the outer layer. For a double sided board (1/16 or 1/32") the additional stray capacity is small compared with the 22pF caps.

As Short Circuit has said, any reasonable layout will work, but it's not difficult, I'd make the change.

Jim

[exscape]

C11, C12 and the crystal (which is inductive at the frequency of oscillation) form a tuned circuit. For minimum radiation or pickup, ensure that the area enclosed by currents circulating in this loop is minimised.
To do this place C11 & 12 alongside the crystal with their earthed ends close together in the middle.
Personally I would use an earth plane unless it's a multi-layer board with a very thin (0.005") dielectric under the outer layer. For a double sided board (1/16 or 1/32") the additional stray capacity is small compared with the 22pF caps.

As Short Circuit has said, any reasonable layout will work, but it's not difficult, I'd make the change.

Jim

Something

? (Quick throw-together, I'll reposition slightly/clean it up if it's better than the previous one.)
Note the connection between the crystal ground and the decoupling-cap - OK?

[jimmc]

I'd be happy with that.
With regards to the decoupling cap, either merge the 'GND' track into the ground plane or only connect it to the ground pin via the track.
I've a slight preference for merging but I'm sure either would work.

Jim

[exscape]

I'd be happy with that.
With regards to the decoupling cap, either merge the 'GND' track into the ground plane or only connect it to the ground pin via the track.
I've a slight preference for merging but I'm sure either would work.

Jim

Alright, thanks!
I ended up with this:

Mmmm, symmetry...

[dfnr2]

That will probably work, but you can do better, especially for a 2-layer design.  Flip both caps 180 degrees so the clock side of the caps are close (not the grounds), and run both lines as close together as possible from the pins to the crystal.  That will minimize loop area.  You could further minimize the loop area if you stagger the caps to bring the inner pads closer to an in-line position, resulting in bringing the outside pads closer together as well.  Have them branch out only when they reach the crystal pads.  Don't cut out the ground plane below the crystal circuit.  There shoudl be no copper pour between the two limbs of the clock circuit.  (Since the leads should be too close together.) For a 0.062" 2-layer design, the bottom ground plane is not really effective, but cutting out the ground plane is--at best--unhelpful.

Also, put proper fat traces from the pads to ground.  Place a at least one thick 30 mil or bigger trace to the ground plane from each far corner of each ground pad (use a couple of vias connected by imperceptibly short traces, if you have a 4-layer design. You can tent over the vias to prevent solder from wicking down them from the pad.)  The three thermals from each grounded cap pad to the inner copper as you have it are low inductance to nowhere , since the inner copper is not connected to anything but the ground pads.  The slim thermal to ground is high inductance. 

[exscape]

That will probably work, but you can do better, especially for a 2-layer design.  Flip both caps 180 degrees so the clock side of the caps are close (not the grounds), and run both lines as close together as possible from the pins to the crystal.  That will minimize loop area.  You could further minimize the loop area if you stagger the caps to bring the inner pads closer to an in-line position, resulting in bringing the outside pads closer together as well.  Have them branch out only when they reach the crystal pads.  Don't cut out the ground plane below the crystal circuit.  There shoudl be no copper pour between the two limbs of the clock circuit.  (Since the leads should be too close together.) For a 0.062" 2-layer design, the bottom ground plane is not really effective, but cutting out the ground plane is--at best--unhelpful.

Also, put proper fat traces from the pads to ground.  Place a at least one thick 30 mil or bigger trace to the ground plane from each far corner of each ground pad (use a couple of vias connected by imperceptibly short traces, if you have a 4-layer design. You can tent over the vias to prevent solder from wicking down them from the pad.)  The three thermals from each grounded cap pad to the inner copper as you have it are low inductance to nowhere , since the inner copper is not connected to anything but the ground pads.  The slim thermal to ground is high inductance.

D'oh - not quite what I wanted to hear at this point, as it's been too late to change anything for 3 hours now! 
I guess it'll still *work* as is, though? And hell, if not, that's not the end of the world either, as I could use the internal oscillator if need be.

[dfnr2]

I would be very surprised if it doesn't work.  The suggestions were for reducing RF emissions.  If it doesn't start, the various causes and fixes would likely be independent of footprints and layout.

[jimmc]

Don't worry it will work, the layout is not that critical.

I still prefer the layout the way it is, a slight improvement would be to run the tracks vertically from the caps to xtal pads but the difference is not significant.

I've been involved in RF design for over forty years now so I'm a bit set in my ways; I can't guarantee that that the layout I suggested is the absolute best, but I am certain that it will work well.

Jim

[dfnr2]

There are a lot of resources on the web as well.  A quick search turned up This link which shows a picture similar to what I was describing.  There are plenty of other examples out there, and, increasingly, this forum seems to have active discussions on PCB layout issues.  The common theme is keeping the loop area small, and the leads short.  Long leads adjacent to a ground pour will increase capacitance much more than a ground plane on a two layer board, and could affect startup time, but for a 16 MHz oscillator is unlikely to have any effect.

And Jimmc is correct, the layout will not interfere with function of the oscillator at 16 MHz.  It can potentially affect EMC, though, but that's a whole different topic.