Author Topic: JLCPCB having an "interesting" attitude to reading text on layers  (Read 6905 times)

0 Members and 1 Guest are viewing this topic.

Offline Fire Doger

  • Regular Contributor
  • *
  • Posts: 207
  • Country: 00
  • Stefanos
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #25 on: October 21, 2019, 10:55:56 am »
I am relative new to pcb manufacturing but never thought that they will consider the thickness of a line for outline, every 3D viewer uses the middle :-//

On the other hand for slot cutouts it's a little blur to me.
For ex. square cutouts with all sides bigger than 0.8mm (pretty standard mill tool diameter and cheap afaik) I define cutout by making a square (with 0.8 arcs in corners) and use the center of the line as the edge for consistency.
I guess the same way they offset their path for complex outline shapes will apply and at this cuts but will offset inside (Am I wrong?)

But in case I want a 0.8 width cutout for panelization I use a single line because I imagine that for cnc it's a single pass.
I guess it will require more modification if I design a square with thickness same as the toolhead or the mill head will make 2 passes in same path. (And it's so more time consuming designing squares for every cut)
But this deviates from above method so I am not sure if I am doing it according to standard... :-//
 

Offline james_s

  • Super Contributor
  • ***
  • Posts: 21611
  • Country: us
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #26 on: October 21, 2019, 05:16:26 pm »
I think that only matters for the manufacturing process. When it comes to designing the board you should assume a zero width line for cuts.
 

Offline cgroen

  • Supporter
  • ****
  • Posts: 631
  • Country: dk
    • Carstens personal web
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #27 on: October 22, 2019, 07:27:15 am »
Let me ask a question. Not meant to be personal, or suggesting anything.

How long have you guys been doing PCB design?

If 5-10 years then I can believe procedures have changed within that time.

Since 1990, and have never been doing anything else than middle of line for outline (since using CAD, after approx 1992). In the "tape days" I used the inside of the tape as you suggest, but that was due to the implications involved...)
 

Offline rrinker

  • Super Contributor
  • ***
  • Posts: 2046
  • Country: us
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #28 on: October 23, 2019, 06:30:08 pm »
 I haven't been designing PCBs for long at all, in fact most would probably laugh at the noobishness of my designs. However, I do have machine shop experience with CNC machine tools and it's normally assumed that a toolpath shown on the drawing or on the machine (very few of the machine we had back when I did this work had graphical displays, not like modern ones) meant that the cut point was the center line and the rest was the tool diameter. SO if you wanted to cut off 100mm length of material, using a cutter with a 2mm diameter, the line had to be at 101mm to result in the finished product having a 100mm length.
 Probably not explaining my thought process correctly, but this is also something I learned as a child, learning how to saw wood. Always mark which side is the scrap piece, so you place the saw blade on the proper side of the line so the finished piece will be the size you want, not the size you want less the width or partial width of the saw blade.
 It sounds like I am actually agreeing with the OP, however, it is not the job of the Gerber to specify the tool path, but to specify the desired dimension. The CAM software provides the tool compensation to the finished product ends up with the specified dimension regardless of the size of the tool bit being used.

 

Offline mac.6

  • Regular Contributor
  • *
  • Posts: 225
  • Country: fr
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #29 on: October 24, 2019, 08:58:36 am »
Using middle of lines for dimension is pretty much the norm in the CAD industry. And when I say norm, is it probably written explicitly in some ISO/ANSI norm.
 

Online SiliconWizard

  • Super Contributor
  • ***
  • Posts: 14478
  • Country: fr
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #30 on: October 24, 2019, 01:21:04 pm »
I think so too.

Some people seem to assume that the line thickness would somehow represent the milling bit diameter to be used - hence the reasoning of the inner edge being the final result - but I haven't seen this in use for ages.

The "middle" is just the line position. The thickness conveys no useful information AFAIK, except of course for PCB traces.
 

Offline peter-hTopic starter

  • Super Contributor
  • ***
  • Posts: 3698
  • Country: gb
  • Doing electronics since the 1960s...
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #31 on: October 25, 2019, 03:50:12 pm »
Clearly the reason I have got away with doing it "wrong" is because I used companies (including Chinese ones) where somebody visually examines the layers and reads the text on them :)

It was only when I used a super cheap company that this happened.

If nobody looks at the layers, how do they e.g. know which is the top layer and which is the bottom layer?

And how would you do a board which has a lot of tracks within a plane? Normally that's done by dropping a polygon into the plane, to clear out the required area within it, and then creating another layer (on a 4L board with 2 planes, this would be Layer 3) with the tracks on it, and on that layer you put a text note to merge that layer with the plane. So, somebody has to read this, to do it.
Z80 Z180 Z280 Z8 S8 8031 8051 H8/300 H8/500 80x86 90S1200 32F417
 

Offline cgroen

  • Supporter
  • ****
  • Posts: 631
  • Country: dk
    • Carstens personal web
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #32 on: October 25, 2019, 03:53:32 pm »
If nobody looks at the layers, how do they e.g. know which is the top layer and which is the bottom layer?

And how would you do a board which has a lot of tracks within a plane? Normally that's done by dropping a polygon into the plane, to clear out the required area within it, and then creating another layer (on a 4L board with 2 planes, this would be Layer 3) with the tracks on it, and on that layer you put a text note to merge that layer with the plane. So, somebody has to read this, to do it.

Because of the names of the files. Has so far worked for me for more than 100 projects submitted to JLCPCB (and also for PCBWay and ALLPCB)

I use:
 

Offline wraper

  • Supporter
  • ****
  • Posts: 16865
  • Country: lv
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #33 on: October 25, 2019, 03:58:31 pm »
Clearly the reason I have got away with doing it "wrong" is because I used companies (including Chinese ones) where somebody visually examines the layers and reads the text on them :)
It could also be that in some cases you just did not notice that PCB was larger than intended. Simply because there was no tight mechanical constraint around the board.
 

Offline nctnico

  • Super Contributor
  • ***
  • Posts: 26907
  • Country: nl
    • NCT Developments
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #34 on: October 25, 2019, 05:08:18 pm »
Clearly the reason I have got away with doing it "wrong" is because I used companies (including Chinese ones) where somebody visually examines the layers and reads the text on them :)

It was only when I used a super cheap company that this happened.

If nobody looks at the layers, how do they e.g. know which is the top layer and which is the bottom layer?
Simple: Put a number on each layer. 1=top, the last one is bottom.

Quote
And how would you do a board which has a lot of tracks within a plane? Normally that's done by dropping a polygon into the plane, to clear out the required area within it, and then creating another layer (on a 4L board with 2 planes, this would be Layer 3) with the tracks on it, and on that layer you put a text note to merge that layer with the plane. So, somebody has to read this, to do it.
That is the wrong way to do it. Just make sure the artwork for 1 layer is in 1 gerber. Having the PCB house doing post processing like this is asking for trouble. A plane with traces isn't a plane. I never use pure plane layers but always put polygons on layers; I find having to use inverse drawing on one or more layers confusing and thus prone to errors.

Using two artworks for one layer is also likely to get you in trouble when an assembler prefers an ODB+ container.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline grbk

  • Contributor
  • Posts: 49
  • Country: us
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #35 on: October 25, 2019, 05:22:24 pm »
And how would you do a board which has a lot of tracks within a plane? Normally that's done by dropping a polygon into the plane, to clear out the required area within it, and then creating another layer (on a 4L board with 2 planes, this would be Layer 3) with the tracks on it, and on that layer you put a text note to merge that layer with the plane. So, somebody has to read this, to do it.

Perhaps I'm misunderstanding you. Are you saying that for a copper layer that has both a plane and traces, you would submit two separate gerber files, one with the traces and one with the plane, and then write in text that they should be merged into one copper layer?

You say "Normally that's done" but normally done by whom?? And why? What tool are you using? I have never in my life heard of anything remotely similar to that.
 

Offline james_s

  • Super Contributor
  • ***
  • Posts: 21611
  • Country: us
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #36 on: October 25, 2019, 05:46:02 pm »
I've never seen anything other than one single copper layer per layer of the board. If you have a combination of traces and a pour, they would all just be drawn on the gerber file for that layer, regardless of the process by which you created it.
 

Offline bpiphany

  • Regular Contributor
  • *
  • Posts: 129
  • Country: se
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #37 on: October 27, 2019, 03:47:32 pm »
There actually is a gerber tag for drawing in "negative", no need to do multiple files and "merge" them by hand.

Doing planes this way (a big plane with negatives, and later tracks on top) would however be prone to creating copper island, and I believe most CAD packages will do it in different ways.
 

Offline peter-hTopic starter

  • Super Contributor
  • ***
  • Posts: 3698
  • Country: gb
  • Doing electronics since the 1960s...
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #38 on: October 27, 2019, 06:03:36 pm »
I would be interested to know how you do tracks within a plane, and end up with a single gerber layer.

Obviously one way is to not have a "plane" and instead construct the desired areas of the plane with filled polygons / pours / etc.
Z80 Z180 Z280 Z8 S8 8031 8051 H8/300 H8/500 80x86 90S1200 32F417
 

Offline james_s

  • Super Contributor
  • ***
  • Posts: 21611
  • Country: us
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #39 on: October 27, 2019, 06:11:31 pm »
Easy, I draw my tracks then outline a copper pour, then I outline any keepout areas, then I tell it to fill the copper pour(s) and the software (KiCad in my case) does its thing. The copper on that side is all one layer before I even think about exporting gerbers, I do not do any manipulation of the gerbers themselves at all, they are the final output I have the software generate when the board is finished.

Modern board design is not like laying everything out manually with tape, you don't have to think about the intermediate steps, you let the software figure all that out.
 

Online ataradov

  • Super Contributor
  • ***
  • Posts: 11260
  • Country: us
    • Personal site
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #40 on: October 27, 2019, 06:17:30 pm »
Yes, I don't see why would you even think about gertbers. It is just a garbage, but standard interchange format at this point.

EDAs will do whatever they need to do to make your chopped planes appear fine.
Alex
 

Offline james_s

  • Super Contributor
  • ***
  • Posts: 21611
  • Country: us
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #41 on: October 27, 2019, 06:20:32 pm »
Just as an example, here's the top copper layer of a board I did some time back, this is a single layer. I laid out the traces, then put a pour boundary around the edge of the entire PCB, then placed several keepout zones on top of that. The software knows what net the pour is connected to and will automatically avoid pouring copper within a set distance of traces in any other net. When I was finished with the layout one of the last steps was to tell it to fill the pours.
 

Offline Mr. Scram

  • Super Contributor
  • ***
  • Posts: 9810
  • Country: 00
  • Display aficionado
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #42 on: October 28, 2019, 05:25:26 pm »
Clearly the reason I have got away with doing it "wrong" is because I used companies (including Chinese ones) where somebody visually examines the layers and reads the text on them :)

It was only when I used a super cheap company that this happened.

If nobody looks at the layers, how do they e.g. know which is the top layer and which is the bottom layer?

And how would you do a board which has a lot of tracks within a plane? Normally that's done by dropping a polygon into the plane, to clear out the required area within it, and then creating another layer (on a 4L board with 2 planes, this would be Layer 3) with the tracks on it, and on that layer you put a text note to merge that layer with the plane. So, somebody has to read this, to do it.
It seems you've gotten so wrapped up in a badly formatted design process you can't quite imagine what a well defined process looks like. It's important to understand that what you see at JLPCB is tight process control and tolerances and not a lack thereof. A better defined input leads to a better output. The fact that someone has corrected for sloppy tolerances all those years doesn't mean the input was good.
 
The following users thanked this post: tooki

Offline Pseudobyte

  • Frequent Contributor
  • **
  • Posts: 284
  • Country: us
  • Embedded Systems Engineer / PCB Designer
Re: JLCPCB having an "interesting" attitude to reading text on layers
« Reply #43 on: November 01, 2019, 01:19:41 pm »
If you define your own panel then it is never a question how big your boards are or what line to use.

The only way I see that a thick line could define a board edge is if it was interpreted to be routing. That being said, I never rely on gerber extensions to define what my layers are. The FAB houses that I interact with are very capable. We require checkplots from all of our suppliers. When we get a checkplot back, we verify in a gerber viewer that the layers match and the step and repeats are accurate. Set one set of gerbers to blue, and the other to red. The differences become obvious.
“They Don’t Think It Be Like It Is, But It Do”
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf