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Length matching + impedance matching questions

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VEGETA:
Hello,

I am working on a design using high speed stuff like HDMI 2.0 (6 Ghz) and stuff in the 600 MHz maximum range. ICs used (under NDA  :-//) have different requirements as follows:

1- HDMI 2.0:

to be routed in impedance of 100 Ohms differentially without vias. Of course, from IC to protection diodes from ESD, then to HDMI connector.

I made those as straight and short as possible (still no actual routing though, but tests and placement). However, how to determine 100 Ohm differential impedance between each differential pair using kicad? all videos I saw choose something like 50 ohms for each trace but how to get 100 diff. impedance as required?


2- other stuff like 600 MHz:

they also need to be length matched but I saw the reference board (under NDA  :-//) routing some of them on top layer without vias, and others using vias to bottom layer in 6-layer configuration.

3- DDR3 memory ICs, 4 of them. 1600 class speed total of 16Gbits.

Main IC used which will have all 600 MHz signals is a big BGA, therefore it will have vias to fan out its balls...



Here are my questions:

1- how to determine 100 ohms diff. impedance? also with ensuring same track length.

2- what effect do vias have in this? with respect to impedance and length matching. How to ensure all signals are routed good and the same despite some of them through vias and some others are not. this is important to know since I have to use them due to space constrains.

3- what is the difference between normal impedance matching of diff pairs and diff. impedance?

regards,

nctnico:
How much is your time worth? If this is for work then I suggest to get Orcad PCB designer (at least professional level). This has tools that can largely automate doing the length matching and doing checks for length, phase, impedance and crosstalk. You'll not only need length matching but also phase matching. Likely your large BGA chip also needs compensation for length differences between the chip and the BGA balls.

Ofcourse it is doable with Kicad but it will take a lot more extra time.

Where it comes to determining the differential impedance: you'll need to use a field solver tool for this (included in the Orcad package). From my experience most of the software which uses formulas is way off.

VEGETA:

--- Quote from: nctnico on September 21, 2021, 11:04:32 am ---How much is your time worth? If this is for work then I suggest to get Orcad PCB designer (at least professional level). This has tools that can largely automate doing the length matching and doing checks for length, phase, impedance and crosstalk. You'll not only need length matching but also phase matching. Likely your large BGA chip also needs compensation for length differences between the chip and the BGA balls.

Ofcourse it is doable with Kicad but it will take a lot more extra time.

Where it comes to determining the differential impedance: you'll need to use a field solver tool for this (included in the Orcad package). From my experience most of the software which uses formulas is way off.

--- End quote ---

It is my own project which I hope I can sell it one day, kinda ambitious. I cannot use anything but KiCAD though.

I am interested first to get answers to my questions, then learn how to do the required thing in KiCAD.

I guess in KiCAD I can do length matching and impedance matching by using some website calculators as shown in phill's lab video, if it is reliable enough. but I need to understand how stuff work first, especially vias. vias will be a must in my design due to space constrains, so i need to know.

thanks

nctnico:
Vias are just vias... the routing guidelines for the chip should tell you how many vias are allowed. What is also important is to have a return plane under your impedance matched traces. The best is to have ground but when you go from one plane to the other using a via, there also has to be a via nearby for the return current. If you use a power plane, then you'll need to place decoupling capacitors near the via to handle the return currents. For high speed designs it is recommended to suppress pads on unused layers. Another thing that is important is that the length of the vias should also be taken into account for length / phase matching. You likely need to match to a few tenths of a millimeter so the via length can not be ignored.

But still I ask you to look at this design from a financial perspective: how much is a board spin going to cost you? Are there software tools available to test the quality of the DDR memory interface? For example: NXP has a special tool to verify memory interfaces on their SoCs. Alternatively you can run memtester under Linux (if the device runs Linux).

The layer stackup and geometry are also important. You will want a so called HDI stackup which usually consists of a thin dielectric between top/bottom and ground planes. I recommend to go for a board with 0.09mm width / clearance on all layers for this design. This is doable for most PCB manufacturers but usually not available for pooling. From there you can determine the smallest via you can make. I usually add 5% to the size and go 1 drill size up to get extra margin. You'll likely need 10 layers: top, ground1, signal1, ground2, power1, power2, ground3, signal2, ground4, bottom. In my designs ground2, power1, power2 and ground3 are usually a mixed bag between signal routing, power and ground. You might be able to do without ground2 and ground3 to get an 8 layer design but it will complicate DDR3 routing because you have to use power as the return path.

VEGETA:
My approach is to have 4 layers (ref board had 6 but it contains many stuff I don't require). stack is top-gnd-gnd-bottom. most traces are on top layer of course while most caps\resistors may go to bottom layer except those required for top traces. not a strict rule anyway.

power is done via a 20 watts recom ac-dc power module which delivers 5v, then I make 1.1v, 3.3v, 1.5v using TI switchers + 2.5v, 1.8v, and 1.0v using LDOs since they are rated so little. it is difficult to have a power plane for all of those anyway. most used is 1.1v for the main ASIC and also 1.5v for ram ics.

as for ddr3 memory, no need for what you said. the ASIC requires certain type of ram ICs and i got it exactly as reference board and by the support of the manufacturer. all I need is just connecting the 4 ram ICs to the ASIC and write the SPI software to do the initialization.

I was asking if I for example wanted to route 8 differential pairs @ 600MHz each... I started from the main ASIC on top layer after faning it out, then went through a bit to find I need vias... then I put vias... so far it is length matched and also impedance matched (still to find how to do it deferentially)...

I assume once I put vias, I consider the vias to be a fresh start by themselves, meaning I need to do length matching stuff as if the vias are the true start of the signal. is this correct?

Also, will the vias affect length matching? how about impedance matching? I keep reading that vias are a no-go in this... even in datasheets of my ICs to be used, they write it as not recommended but the reference board used them everywhere on these high speed signals.

The design is a video scaler device  which is capable of up to 4k @ 60 fps from various analog and digital sources. it has one main scaler ASIC (very big BGA) + 2 HDMI transmitters + 1 HDMI receiver (2 ports HDMI to one port 60-bits parallel). all under NDA and capable of 4k60 which is pretty rare till now.

4k60 in this design uses a certain high speed digital video protocol which has 8 differential pairs (lanes) running at 600 mhz each. board size is very limited but will fit if I got vias properly done and so on... using Takachi PF13-4-19W enclosure since I cannot afford custom one.

MCU is going to be RP2040 as raspberry pi pico running arduino bootloader and code which is easiest and can be directly upgradable via usb.

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