The usual method is the create a via breakout structure on the BGA pins you can't reach from the outside. The way you are routing now likely ends up with not being able to reach the inner pads. Also keep room for phase matching. In the bottom picture: the signal from R32 is shorter than R31 so signal R32 will need extra length added to make the phase match. The amount of phase matching required should be in the routing guidelines of the chip.
they way I understand phase matching is that it is length matching between the 2 individual traces. Please correct me if I am wrong. after posting the pictures, I went back and made the phase matching of all these signals, they were adjusted from the upper side near the hdmi tx ic.
most inner pads are ground and I can even route them using the ground plane if I needed.
my concern is that is it good what I did in the pics? most importantly, will vias affect length matching and impedance matching? is my approach of length matching before vias then after vias independently ... is it correct?
I am afraid that vias will ruine the effort but I saw them in the ref board which uses the same ICs... also, they are inevitable due to BGA and small space. routing some of them using layer 2 which is ground plane is doable since it will also have a very near and close ground plane under it which is layer 3.
In general there are two categories of phase matching, 'static' and 'dynamic'. Static is mainly to do with overall time of flight/trace length, while dynamic is concerned with "local" matching of signal trace lengths, using fiber weave, serpentine routing, etc. to make sure the electrical signal matches between the pair as close as possible along the entire routing.
As nctnico said, vias are vias, in terms of phase matching they behave similar to traces. Some things you would need to watch out for are (in no particular order):
1. Via 'stubs', when you route a signal to an inner layer, you can end up with a "stub" of via that is unused at the end, that can cause unwanted signal integrity issues.
2. Different velocity of signal between inner and outer layers (microstrip vs. stripline signals have different velocities due to the different surrounding media)
3. Ground plane matching/return path. Like nctnico said, you need to make sure your signal has a complete and unbroken return path on the capacitively coupled GND (or in some cases power) plane. Not heeding this can cause some bad signal integrity issues.
Since you said your board is just 4 layers this makes it easier, just make sure there is a solid ground plane coverage.
In regards to your images:
1. Are those meant to be AC caps in image 1? Usually those should be place as close as possible to the transmitter source.
2. You should consider using smoother angles for high speed routing instead of 45 degree, but some suites don't let you do this.
3. The vias under the BGA look good, but the other vias look awkwardly routed. You should try to make sure that your traces are entering the via perpendicular to the side, rather than at an angle. This is mainly for production reasons. Attached is what they normally look like.