Linear voltage regulators - working principle

[joniengr081]

I am trying to understand the functionality of linear regulators. I have attached the fundamental circuit of linear regulator.

Can someone please explain how does the circuit work ?

I am also wondering where the V-Ref comes from ? Consider two following two cases.

Vin = 5.0 V
Vout = 4.0 V
Iout = 1 A

Vin = 3.3 V
Vout = 2.5 V
Iout = 1 A

Would V-Ref be the same for both cases or not ?

[T3sl4co1l]

Explain at what level -- are you familiar with op-amp analysis? BJT operation? Circuit analysis in general? A high-level explanation, or in thorough detail down to device characteristics and control theory?

Tim

[joniengr081]

Yes, I am familiar with operational amplifier and circuit analysis in general using basic electronics devices like PNP/NPN BJT transistors, operational amplifiers and diodes. Therefore, I am interested to learn how the components inside the linear regulator works to regulate the output voltage. 

Can some please explain the internal functionality ? Thanks in advance. 

Also is V-Ref fixed for a device ? I mean by caning Vin/Vout in the same device. Would V-Ref remains the same per device ?

[Doctorandus_P]

First thing. Forget the misnomer that inputs of an operational amplifier always have the same voltage. This assumption does not work when the thing gets saturated, is used as a comparator and on other instances.

A simple and effective way to look at an opamp is: If the voltage at the non inverting input is higher then the voltage at the inverting input, then the output goes to a higher voltage. If the voltage ata the non-inverting input is lower then the other input, then the output goes to a lower voltage. That is all there is. Often a balance is reached (and both inputs will have the same voltage) but not always.

For the analysis.
1. Assume Q1 is "off" at startup.
2. Non inverting input is at Vref.
3. Because Q1 is "off", non-inverting input is also at zero volt.
4. Non inverting input has highest voltage, and thus output of the opamp will rise (slew rate limited).
5. Base voltage of Q1 will also rise, as a result emitter of Q1 follows the base voltage (minus 600mV).
6. Vin = emitter voltage and will also rise.
7. Inverting input of opamp will also rise, (With fixed ratio because of R1 and R2).
8. This continues until the voltages at the input of the opamp are the same.
9. If the output of the opamp would rise further, then the non-inverting voltage would be higher then the inverting input.
10. ... And that would result in the output voltage getting lower again.
11. Thus the circuit stabilizes itself.

[joniengr081]

Here is the link from which I get the circuit diagram attached in the first post. 
https://www.digikey.com/en/maker/tutorials/2016/introduction-to-linear-voltage-regulators

I understand that if the voltage at the non-inverting input (v_ref) is higher then the voltage at the inverting input (v_adj), then the output of the operational amplifier goes to a higher voltage. This will happen which the output voltage drops. But then in the case of output voltage drops, the high output of the operational amplifier will turn on the transistor Q1, right ?

And if the voltage ta the non-inverting input (v_ref) is lower then the voltage at the inverting input (v_adj), then the output of the operational amplifier will be low. This will happen when the output voltage increases that makes the voltage divider v_adj slightly higher then the v_ref causing the output of the operational amplifier low. But then this will turn off the transistor Q1, right ?

[joniengr081]

I think I am getting it now.

1- The linear regulator output voltage v_out is zero in the start.
2- The voltage divider voltage v_adj across R1, will also be zero which is connected to inverting input of the operational amplifier.
3- The v_ref is connected to non-inverting input of the operational amplifier.
4- The output of the operational amplifier will be high as vin+(v_ref) > vin-(v_adj).
5- The NPN transistor Q1 will conduct because the high output of the operational amplifier will turn on the the NPN transistor Q1.
6- Assuming the base to emitter voltage 600 mV (which is usually called drop out voltage in linear regulator).
7- The output voltage of the linear regulator start increasing that will also increase the voltage divider voltage v_adj across R2, which is connected to inverting input of the operational amplifier.
8- As the output of the linear regulator increase further, this will increase vin-(v_adj) compared to vin+(v_ref), causing the output of the operational amplifier low which will turn off the NPN transistor Q1.
9- The capacitor across the output load C2 will stabilize the output voltage through it's dis-charging during the time when NPN transistor Q1 is off.
10- As the output of the linear regulator start decreasing, this will lower the v_adj causing vin+(v_ref) > vin-(v_adj), which turn on the NPN transistor Q1 through the high output of the operational amplifier. This is how the linear regulator stabilize the output.

[joniengr081]

Just last thing. The output current of the linear regulator is limited by the current the transistor is rated for, right ?

[mikerj]

Just last thing. The output current of the linear regulator is limited by the current the transistor is rated for, right ?

The answer depends on your context:
There is no current limiting in this circuit, a short circuit could easily destroy the pass transistor.  The limit for safe operation is determined by the "Safe Operating Area" (SOA) of the transistor, which is a combination of maximum collector current, maximum Collector-Emitter voltage, power dissipation and secondary breakdown limits.  You will find a chart in most transistor datasheets that show this area.  Even when operating within the SOA, you must provide sufficient cooling to the transistor to keeps it's junction temperature under the maximum permitted value (preferably well under).