Logic Simulator with Propagation Delay Capabilities

[nctnico]

Either way, using a simulator which is part of an FPGA / programmable logic toolchain is completely the wrong tool to use. The 74xx models are just there for people who like to draw schematics using 74xx logic chips. But there is absolutely no connection to the timing behaviour of actual 74xx chips.

[asmi]

Either way, using a simulator which is part of an FPGA / programmable logic toolchain is completely the wrong tool to use. The 74xx models are just there for people who like to draw schematics using 74xx logic chips. But there is absolutely no connection to the timing behaviour of actual 74xx chips.

You can absolutely make models which would behave exactly as real chips timing-wise. Oh, and if your logic is even somewhat complex, you would do yourself a great favor by running functional sims before ever touching real chips as logic mistakes are much easier to find and fix in simulations than once you made a PCB and soldered everything, and people tend to grossly overestimate their ability to "run sims" in their heads during circuit design and got it right on a first try without any logic bugs.

[nctnico]

Either way, using a simulator which is part of an FPGA / programmable logic toolchain is completely the wrong tool to use. The 74xx models are just there for people who like to draw schematics using 74xx logic chips. But there is absolutely no connection to the timing behaviour of actual 74xx chips.

You can absolutely make models which would behave exactly as real chips timing-wise.

Why would you do that for tools which don't have those models available while there are other tools (Microcap for example) which do have those models right out of the box? It is just extra work which has been done already by people who thought about what would be useful and what is not. And Pspice based simulators can simulate interactions with analog circuitry as well. Think about adding some logic to do cycle-by-cycle current limiting to a PWM controller. There really is no upside to use simulators targeted at FPGAs / programmable logic if your goal is to simulate 74xx chips.

[iry100fan]

I have been playing around with Micro-Cap 12.2.0.5.  This looks very promising.  It seems to give me the results I am looking for, is fairly intuitive to use and very easy to customize the timings.

[asmi]

There really is no upside to use simulators targeted at FPGAs / programmable logic if your goal is to simulate 74xx chips.

1. There is no such thing as "simulators targeted at FPGAs/programmable logic". HDL is the Hardware Description Language, and - believe or not - 74xx chips are hardware. You are too caught up with the false impression that HDL == FPGA, and should probably learn how HDLs are used outside of FPGAs - which is what they were actually originally created for, what is technology library and how they are used to map HDL constructs into the actual physical cell structures in a silicon.
2. Logic-level simulations are much faster than pspice presicely because they ignore a whole bunch of physical phenomena which are ultimately irrelevant to the result you are looking for - which is a logic calculation. It's a very useful abstraction for a functional verification - you don't need to know which current flow where if you use the wrong kind of gate in your logic.

[nctnico]

There really is no upside to use simulators targeted at FPGAs / programmable logic if your goal is to simulate 74xx chips.

1. There is no such thing as "simulators targeted at FPGAs/programmable logic". HDL is the Hardware Description Language, and - believe or not - 74xx chips are hardware. You are too caught up with the false impression that HDL == FPGA, and should probably learn how HDLs are used outside of FPGAs - which is what they were actually originally created for, what is technology library and how they are used to map HDL constructs into the actual physical cell structures in a silicon.

No, I'm not caught up at all. I just see that using a HDL simulator targetted at FPGA / programmable logic would incur a lot of extra work (without any gain) due to lack of behavioural models for 74xx chips. The logic models may be there so 74xx logic blocks can be used in a design which is then mapped onto whatever hardware but those models will only contain the logical model. No delays. It just makes no sense to go this route when there are other tools out there which have the models ready to go out of the box. After all the TS is after simulating the delays for 74xx chips.

On top of all of that, there may be HDL related issues which could cause simulation problems as HDL simulators tend to do 1 step at a time and not iterate until the circuit reaches a stable state. I've been bitten by that in the past by assigning a clock signal which then caused a 1 cycle delay in downstream modules.

2. Logic-level simulations are much faster than pspice presicely because they ignore a whole bunch of physical phenomena which are ultimately irrelevant to the result you are looking for - which is a logic calculation. It's a very useful abstraction for a functional verification - you don't need to know which current flow where if you use the wrong kind of gate in your logic.

No. The better Pspice-ish simulators will use a digital simulator for logical circuits. These are called mixed mode simulators. So there is no difference in simulation speed for a purely digital design.

[free_electron]

2. Logic-level simulations are much faster than pspice presicely because they ignore a whole bunch of physical phenomena which are ultimately irrelevant to the result you are looking for - which is a logic calculation. It's a very useful abstraction for a functional verification - you don't need to know which current flow where if you use the wrong kind of gate in your logic.

Pray tell, how will you simulate a wired-or or wired-and ? Such constructions are common in logic designs with 74xx.

The issue is that the OP is eventually going to build his circuit with actual 74xx chips. There are a lot of things possible with actual chips that can't be done with simulation of just the logic. Certain 74xx chips actual have glitches on their outputs for certain conditions (xor gates ...). Unless you have an actual transistor-level model of the actual chip your simulator will lie to you.

[nctnico]

2. Logic-level simulations are much faster than pspice presicely because they ignore a whole bunch of physical phenomena which are ultimately irrelevant to the result you are looking for - which is a logic calculation. It's a very useful abstraction for a functional verification - you don't need to know which current flow where if you use the wrong kind of gate in your logic.

Pray tell, how will you simulate a wired-or or wired-and ? Such constructions are common in logic designs with 74xx.

The issue is that the OP is eventually going to build his circuit with actual 74xx chips. There are a lot of things possible with actual chips that can't be done with simulation of just the logic. Certain 74xx chips actual have glitches on their outputs for certain conditions (xor gates ...). Unless you have an actual transistor-level model of the actual chip your simulator will lie to you.

Or asynchronous counters like the 74xx93. However, I don't think you need to have transistor models. Detailed behavioural models are good enough. Looking at the model that comes with Microcap it looks like they created a fairly complete behavioural model.

[asmi]

Pray tell, how will you simulate a wired-or or wired-and ? Such constructions are common in logic designs with 74xx.

Big surprise - HDLs support that too! Here you go: https://www.chipverify.com/verilog/verilog-strength

The issue is that the OP is eventually going to build his circuit with actual 74xx chips. There are a lot of things possible with actual chips that can't be done with simulation of just the logic. Certain 74xx chips actual have glitches on their outputs for certain conditions (xor gates ...). Unless you have an actual transistor-level model of the actual chip your simulator will lie to you.

That still does not invalidate HDL simulations as the first line of defense against logical bugs. No simulator is ever perfect, and continued persistence of silicon bugs in new chips is a proof positive of that. But since doing a silicon revision takes months and up to millions of $$$, while running sims are orders of magnitude less, it totally makes sense to invest small amount of time and resources for a chance to catch issues which would otherwise definitely force a silicone revision.

[free_electron]

Or asynchronous counters like the 74xx93.

oh yes. Or bastards like NXP that implement them so they are "logically" the same but internally are constructed as synchronous....

I remember an issue in a design that used a 4040 ripple counter. It was a TV testpattern generator. It used a chain of those counters to generate the line and frame via a diode matrix. The design worked perfectly fine with an NXP HEF4040. Stick anything else in there and the pattern went all wonky. Reason ? the HEF4040 internally is designed as a  synchronous counter and does not glitch in its output. Anything else does glitch ( it is a ripple counter after all. They glitch while counting...) and cause premature resets in the count chain.

There is NOTHING in the datasheets that explains that....

[free_electron]

Pray tell, how will you simulate a wired-or or wired-and ? Such constructions are common in logic designs with 74xx.

Big surprise - HDLs support that too! Here you go: https://www.chipverify.com/verilog/verilog-strength

That is something totally different. That is the charge in a node. It controls the drive strength ( and thus the rise/fall time. )

Wired or/and  is tying outputs of gates directly to each other. This requires logic with open collector or open emitter. There are plenty of those things in the 74xx series . You'll need to make constructions in verilog that set a value of 'Z' instead of '1' . Verilog supports 'Z' (high impedant) and 'X' (unknown). The problem is that, in test benches a 'Z' typically resolves to '0'. The testbench only supports 2-state values. Whereas the 'Logic' type supports 4-state. I have gotten burned on such things... It may have changed now with newer versions of systemverilog.

This is the problem with simulators. They impose additional problems that you need to be aware of and take into account. You spend more time working around the misery than it takes to breadboard the damn thing !

[asmi]

That is something totally different. That is the charge in a node. It controls the drive strength ( and thus the rise/fall time. )

Did you read far enough to reach pullups/pulldowns?

Wired or/and  is tying outputs of gates directly to each other. This requires logic with open collector or open emitter. There are plenty of those things in the 74xx series . You'll need to make constructions in verilog that set a value of 'Z' instead of '1' . Verilog supports 'Z' (high impedant) and 'X' (unknown). The problem is that, in test benches a 'Z' typically resolves to '0'. The testbench only supports 2-state values. Whereas the 'Logic' type supports 4-state. I have gotten burned on such things... It may have changed now with newer versions of systemverilog.

This is the problem with simulators. They impose additional problems that you need to be aware of and take into account. You spend more time working around the misery than it takes to breadboard the damn thing !

I've never seen a simulator that does what you're describing. All sims I've ever used properly display all four states. But if you use pullup/pulldown, you will always see a valid digital value as Z with pullup will be logic one, and the same with pulldown will be logic zero.

[tggzzz]

https://logicmadness.com/verilog-strengths/

[RoGeorge]

Would be great if the software have a GUI to layout and connect the gates but I can do HDL if necessary.  Native Linux software would be preferable

I wouldn't go for HDL tools unless the end project must be put in an FPGA or something.  My default go to tool os LTspice.  Not Linux native, but it works just fine under Linux (with WineHQ).  Has a nice GUI and waveform plotter, free to use, can simulate analog, tons of SPICE models online that can be used directly (or adapted) to LTspice.  Has a few ready made libs for most of the 74xx logic series (including N, LS, HC, etc., download and install the Bordodynov libs for LTspice).

- install wine, sudo apt install wine, or alike
- download and install LTspice (I like LTspice XVII, because LTspice 24 is under developement and it keeps shuffling/renaming GUI menus and such) https://ltspice.analog.com/software/LTspice64.exe
- download and install the Bordodynov libs (there are many ways to do that, random first link popped at a search:  http://bordodynov.ltwiki.org/ , or https://www.eevblog.com/forum/eda/ltspice24-importing-the-a_bordodynovs-lib-and-examples/ , etc.)

Then make a new directory for your project, copy the needed models locally (so your project is self contain, and years later, after all the libs have changed, your project will still produce the same results as today), and simulate your circuits.

If you want to ask or post simulation, attach the zip with your directory project, with the .asc and the models/libs/symols you were using, and eventually the .plt if you want to plot certain signals by default (these .asc, .lib, .sym and .plt files should be a few kB at most).  Don't add the .raw, or any other unneeded/intermediary files.

Another thing to know, there are parameters that can be set manually:

Spice Directives of digital properties in LTspice

Code: [Select]

Property Spice Directive
OUTPUT HIGH VOLTAGE Vhigh
OUTPUT LOW VOLTAGE Vlow
INPUT THRESHOLD Ref
RISE TIME Trise
FALL TIME Tfall
PROPAGATION DELAY td
You didn't say which family of 74xx you plan to use, so I won't go into more details.  The thing is, find the library you need, inspect the models, and if they don't fit, adjust them.


And in case you want to simulate HC ring oscillator, only a couple of days it happened that I've measured a 3 gates ring oscillator made with a SN74HC00.  It oscillates starting from a Vcc as low as half a volt! 


From https://www.eevblog.com/forum/chat/1000001-santa-scanner-vco-confirmed-have-you-been-naughty-or-nice/msg6139043/#msg6139043

My advice, don't fool around too much with simulation (I did that mistake already, and now I regret all the time wasted with simulation and with library/parameters fiddling).  Particularly if your schematics makes use of the analog properties of the gates, because the simulation results simply won't match reality well enough.  Instead of simulating, build the circuit and measure it, it will take 10 times less, and the results will be 100 times more accurate.

For the fun of it, here's the same ring oscillator simulated.  At 2V, the measured frequency was less than 7.2MHz, while in simulation it oscillates at about 6.1MHz.  At 6V, measured frequency was 37.9MHz, while the simulated gives 22.6MHz. 

[nctnico]

For the fun of it, here's the same ring oscillator simulated.  At 2V, the measured frequency was less than 6.1MHz, while in simulation it oscillates at about 7.2MHz.  At 6V, measured frequency was 37.9MHz, while the simulated gives 22.6MHz. 

What do you expect? If you check the datasheet, you'll see delays vary a lot over temperature and device variation. The only thing guaranteed are maximum delays over voltage and temperature. The simulator typically uses the worst case delay to make sure a simulated circuit will work at the worst case condition (which is what you want).

[RoGeorge]

OK, but how about the other surprises, it starts oscillating at about 0.4-0.5V (at about 250Hz) and it still works at 10V (this is more than the absolute max 7V from the datasheet, and the measured fosc was 50MHz+). 

Not to say, simulated circuits, simulated fun.  Want real fun?  Build real circuits! 

[nctnico]

OK, but how about the other surprises, it starts oscillating at about 0.4-0.5V (at about 250Hz) and it still works at 10V (this is more than the absolute max 7V from the datasheet, and the measured fosc was 50MHz+). 

Not to say, simulated circuits, simulated fun.  Want real fun?  Build real circuits! 

Well, the trick with simulation is to know the limitation. But there are also things you can do easely with a simulator. Like sweeping through temperatures and doing tolerance sensitivity simulations. This can often lead to new insights in how feasible a circuit it and how produceable it is. Things may work on a breadboard in a lab but when you produce 1000 units you might run into nasty surprises due to temperature and component variations.

[tggzzz]

What do you expect? If you check the datasheet, you'll see delays vary a lot over temperature and device variation. The only thing guaranteed are maximum delays over voltage and temperature. The simulator typically uses the worst case delay to make sure a simulated circuit will work at the worst case condition (which is what you want).

For hold time violations and static hazard glitches, you need minimum times.

With al simulations you have to be very suren the models you are using are appropriate to whatever you are looking for. That's famously true for opamp models, but it also applies to digital logic.