LTspice race condition in JK flip flop

[Faringdon]

Hi,
I am getting race condition problems in the LTspice sim of a Toggle type JK Flip flop as attached.
Do you know the best way to avoid this?

[langwadt]

Hi,
I am getting race condition problems in the LTspice sim of a Toggle type JK Flip flop as attached.
Do you know the best way to avoid this?

for some reason FF in ltspice have zero delay

right click and add something like Td=1ns to the "spiceline"

[Ian.M]

He's already done that but has Tripdt set too high.

However you cant make a JK flipflop that way as that circuit is gated, not clocked.  Therefore the outputs keep toggling as fast as they can so long as the gate is active (low).  To fix this and make it edge triggered, so it toggles ONCE per clock cycle, you need a master-slave flipflop pair.  See https://www.falstad.com/circuit/e-jkff.html

[Faringdon]

To fix this and make it edge triggered, so it toggles ONCE per clock cycle, you need a master-slave flipflop pair.  See https://www.falstad.com/circuit/e-jkff.html

Thanks, i did this, and i still have race condition, sorry i must have done something wrong...as attached

[Ian.M]

As LTspice logic A devices don't respect the .tran startup modifier, even though their outputs act as sources, and don't have a Vcc supply pin, so cant be powered from a source that does, the two NAND SR latches start in a race condition, acting as metastable ring oscillators.   This is a simulation artifact due to SPICE quantizing the signals in the time domain and ideally matched components. In real life such latches are vanishingly unlikely to oscillate for many cycles after powerup as even on the same die the propagation delays will vary slightly.  Break the race condition by altering the propagation delay of one of the gates in each latch slightly, (by min. 1x Tripdt).  N.B. it may still glitch during the first full clock cycle.

I've redrawn the schematic for clarity, with net labels (for ease of probing), with all gate propagation delays and risetimes visible (N.B. Tfall defaults to Trise if not set) and with separate sources for the J and K inputs, and removed your explicit grounds as the A device gates default to using global node 0 (GND), so you only need to connect their ground pin if you need them referenced to another net. 

All gates have their hidden parameters set as:

Code: [Select]

Vhigh=3.3 Vlow=0 Ref=1.5
Tripdt=5n
I applied the above propagation delay offset fix and it no longer oscillates.