Matching/calculating propagation delay of internal traces and external traces

[Northy]

I'm routing a board where I need to match some internal traces and external traces. I know ideally they should be on the same layer, they I could just match the lengths, no. of vias etc, but the routing just isn't viable.

I'm trying to match 'time' here, or I guess propagation delay is a better term. As signals travel faster on external layers, is there a calculator somewhere that I can use to work out what length the external traces need to be to match the internal traces? What other variables do I need from my PCB supplier?

Many thanks,

G

[metrologist]

There's some formulas in this wiki

https://en.wikipedia.org/wiki/Group_delay_and_phase_delay

[Feynman]

First of all you should make sure that you really need matched time/delay. Often times a little skew is totally fine.

But as a rough rule of thumb signal speed on inner layers is about 1,5x10^8 m/s² and signal speed on outer layers is about 1,7x10^8 m/s² (assuming some sort of FR4 board). So one thing you can do is to simply make the inner conductors ~10-15% percent shorter than the outer conductors.

If you need a little more accuracy:
Since propagation speed depends on the relative dielectric constant (and the relative permeability) of the materials around the conductor (usually air, solder mask or some sort of FR4 material), you need those values from your PCB supplier (or the data sheet of the material they are using). The relative dielectric constant for FR4 is usually around 3.8 to 4.5. The tricky part are the outer conductors, because their surrounding material is not uniform. That's where the "effective dielectric constant" comes into play. I think the Saturn PCB Toolkit hat some tools to estimate signal speed on inner and outer layers based on approximation formulas.

For even more accuracy a decent PCB supplier can tell you the propagation speed of each layer. Usually they throw their process knowledge (tolerances, ...) and material properties into a field solver and come up with more accurate values.

But my suspicion is that you don't need this kind of accuracy for matching your trace delay times

[Northy]

Thanks for the replies, very helpful. 

This is a DDR3 connected to a processor, so it's fairly high speed, so I'm just trying to do the best job that I can on it. I have lots of caveats like: the trace length isn't very long to start with, it won't be run 'flat out', etc, but my feeling is if I just take the time now to do the best job I can then that gives the design more margin and will help me sleep at night 

Thanks,

G

[Northy]

Would anyone else have any feedback or suggestions for this? I'm just keen to get this as correct as I can.
I've been advised to try the Saturn Tool Kit, but as I work on a Mac it would be a pain to sort out if it doesn't help. Does anyone else here use it?

Thanks,
G

[Northy]

Does anyone actually know if what I'm trying to do here is even possible?
Is it possible to adjust the length of external tracks to time match internal layer tracks?

Many thanks,

G

[thm_w]

https://www.micron.com/-/media/client/global/documents/products/technical-note/dram/tn4113_ddr3_point_to_point_design.pdf
https://electronics.stackexchange.com/questions/227968/tolerances-for-ddr3-trace-matching
https://electronics.stackexchange.com/questions/239282/is-it-good-practice-to-length-match-all-traces-of-ddr3-or-are-only-data-traces
https://www.nxp.com/files-static/32bit/doc/app_note/AN3940.pdf

Propagation Delay
Propagation delay for inner layers and outer layers is different because the effective die-
lectric constant is different. The dielectric constant for the inner layer is defined by the
glass and resin of the PCB. Outer layers have a mix of materials with different dielectric
constants. Generally the materials are the glass and resin of the PCB, the solder mask
that is on the surface, and the air that is above the solder mask. This defines the effec-
tive dielectric for the outer layers and usually amounts to a 10% decrease in propaga-
tion delay for traces on the outer layers. For the design of JEDEC UDIMMs, a 10% differ-
ence accounts for the differences in propagation of the inner layers versus the outer lay-
ers. If all traces that need to match are routed with the same percentage on the outer
layers versus the inner layers, this difference may be ignored for the purpose of match-
ing timing. Otherwise, this difference should be accounted for in any delay or matching
calculations.
For inner layer propagation, velocity is about 6.5 ps/mm. To match all traces within
10ps, traces must be held within a range of 1.5mm, 60 mils. In most cases, this can be
easily achieved. Most designs tolerate a much greater variation and still have significant
margin. The engineer must decide how much of the timing budget is allocated to trace
matching.

[Northy]

https://www.micron.com/-/media/client/global/documents/products/technical-note/dram/tn4113_ddr3_point_to_point_design.pdf
https://electronics.stackexchange.com/questions/227968/tolerances-for-ddr3-trace-matching
https://electronics.stackexchange.com/questions/239282/is-it-good-practice-to-length-match-all-traces-of-ddr3-or-are-only-data-traces
https://www.nxp.com/files-static/32bit/doc/app_note/AN3940.pdf

Propagation Delay
Propagation delay for inner layers and outer layers is different because the effective die-
lectric constant is different. The dielectric constant for the inner layer is defined by the
glass and resin of the PCB. Outer layers have a mix of materials with different dielectric
constants. Generally the materials are the glass and resin of the PCB, the solder mask
that is on the surface, and the air that is above the solder mask. This defines the effec-
tive dielectric for the outer layers and usually amounts to a 10% decrease in propaga-
tion delay for traces on the outer layers. For the design of JEDEC UDIMMs, a 10% differ-
ence accounts for the differences in propagation of the inner layers versus the outer lay-
ers. If all traces that need to match are routed with the same percentage on the outer
layers versus the inner layers, this difference may be ignored for the purpose of match-
ing timing. Otherwise, this difference should be accounted for in any delay or matching
calculations.
For inner layer propagation, velocity is about 6.5 ps/mm. To match all traces within
10ps, traces must be held within a range of 1.5mm, 60 mils. In most cases, this can be
easily achieved. Most designs tolerate a much greater variation and still have significant
margin. The engineer must decide how much of the timing budget is allocated to trace
matching.

Thank you very much! 

G