Measurement of different PCB trace width with R&S ZLNE-3 VNA / JLCPCB

[cgroen]

Again: Use Sonnet to check your trace geometries!

I tried, installed it, looked at the complexity of it, and removed it again
I "just" need to calculate the impedance of simple tracks, not take over the world (with an 824 MByte application).....

[cgroen]

11,5 mils trace and spacing on FR4 (at Er=4.6) and 1,5mm board gives me 49,6 Ohms, for a coplanar waveguide

That is in AppCAD.

It's a 4 layer, 0.2mm to L2 (GND) in my case (JLC7628 stackup).
According to JLCPCB (https://cart.jlcpcb.com/impedance?_ga=2.33326718.1500801373.1641198313-6221190.1604429483) The Er is 3.8 for a coated track if I understand correctly (and 4.6 for bare copper), or am I wrong ?

[thinkfat]

11,5 mils trace and spacing on FR4 (at Er=4.6) and 1,5mm board gives me 49,6 Ohms, for a coplanar waveguide

That is in AppCAD.

It's a 4 layer, 0.2mm to L2 (GND) in my case (JLC7628 stackup).
According to JLCPCB (https://cart.jlcpcb.com/impedance?_ga=2.33326718.1500801373.1641198313-6221190.1604429483) The Er is 3.8 for a coated track if I understand correctly (and 4.6 for bare copper), or am I wrong ?

The prepreg height (H1) is only 7.1mil in case of conductor on the outside, not 0.2mm. If I use that and the specified \$\epsilon_r = 4.5\$ I get roughly 51 Ohm for a 11.55mil microstrip line. Remember that the impedance calculator on the JLCPCB website is for microstrip, not for CPW.

[cgroen]

11,5 mils trace and spacing on FR4 (at Er=4.6) and 1,5mm board gives me 49,6 Ohms, for a coplanar waveguide

That is in AppCAD.

It's a 4 layer, 0.2mm to L2 (GND) in my case (JLC7628 stackup).
According to JLCPCB (https://cart.jlcpcb.com/impedance?_ga=2.33326718.1500801373.1641198313-6221190.1604429483) The Er is 3.8 for a coated track if I understand correctly (and 4.6 for bare copper), or am I wrong ?

The prepreg height (H1) is only 7.1mil in case of conductor on the outside, not 0.2mm. If I use that and the specified \$\epsilon_r = 4.5\$ I get roughly 51 Ohm for a 11.55mil microstrip line. Remember that the impedance calculator on the JLCPCB website is for microstrip, not for CPW.

According to their spec, the prepreg (for 7628) is 0.2 mm
Their Er is 4.6, and (if I understand correctly) it is 3.8 for "covered" tracks (solder resist)

Edit: Ah, I see where you get the 7.1 mil from, wonder which one is correct ?

[2N3055]

11,5 mils trace and spacing on FR4 (at Er=4.6) and 1,5mm board gives me 49,6 Ohms, for a coplanar waveguide

That is in AppCAD.

It's a 4 layer, 0.2mm to L2 (GND) in my case (JLC7628 stackup).
According to JLCPCB (https://cart.jlcpcb.com/impedance?_ga=2.33326718.1500801373.1641198313-6221190.1604429483) The Er is 3.8 for a coated track if I understand correctly (and 4.6 for bare copper), or am I wrong ?

Well what I calculated is for a standard 2 layer board... numbers are to close to be coincidence.
Is their calculator calculating for wrong stackup?

[cgroen]

11,5 mils trace and spacing on FR4 (at Er=4.6) and 1,5mm board gives me 49,6 Ohms, for a coplanar waveguide

That is in AppCAD.

It's a 4 layer, 0.2mm to L2 (GND) in my case (JLC7628 stackup).
According to JLCPCB (https://cart.jlcpcb.com/impedance?_ga=2.33326718.1500801373.1641198313-6221190.1604429483) The Er is 3.8 for a coated track if I understand correctly (and 4.6 for bare copper), or am I wrong ?

Well what I calculated is for a standard 2 layer board... numbers are to close to be coincidence.
Is their calculator calculating for wrong stackup?

I'm not using the calculator at JLC, I have tried a number of different (that all agree), one of them is Saturn PCB.
Saturn PCB seems to be on line with (microstrip): https://chemandy.com/calculators/microstrip-transmission-line-calculator-ipc2141.htm
And with this (CPW): https://chemandy.com/calculators/coplanar-waveguide-with-ground-calculator.htm

[thinkfat]

The Microstrip calculator at Chemandy gives 49.6 Ohm for the JLC7628 stackup using \$\epsilon_r=4.5\$.

PS: the \$\epsilon_r\$ of the solder mask is not relevant for microstrip, there's no field above the trace to interact with it.

[cgroen]

The Microstrip calculator at Chemandy gives 49.6 Ohm for the JLC7628 stackup using \$\epsilon_r=4.5\$.

Yes. But, is it in fact Er 4.5 or 3.8 to be used if solder resist on the track (I would guess 3.

[thinkfat]

The Microstrip calculator at Chemandy gives 49.6 Ohm for the JLC7628 stackup using \$\epsilon_r=4.5\$.

PS: the \$\epsilon_r\$ of the solder mask is not relevant for microstrip, there's no field above the trace to interact with it.

Sorry, I edited the post while you wrote your reply. You can forget about the solder mask for microstrip. For CPW it might have some influence. But I don't know how much. Surely the effective \$\epsilon_r\$ will not be 3.8.

[cgroen]

The Microstrip calculator at Chemandy gives 49.6 Ohm for the JLC7628 stackup using \$\epsilon_r=4.5\$.

PS: the \$\epsilon_r\$ of the solder mask is not relevant for microstrip, there's no field above the trace to interact with it.

Sorry, I edited the post while you wrote your reply. You can forget about the solder mask for microstrip. For CPW it might have some influence. But I don't know how much. Surely the effective \$\epsilon_r\$ will not be 3.8.

Are you sure ? According to this it has: https://www.multi-circuit-boards.eu/en/pcb-design-aid/impedance-calculation.html

[ogden]

Thermal reliefs are against thombstoning of tiny components or in favor of low cost inferior hand-soldering. As edge-mount SMT sockets are not prone of tombstoning (rofl), you do not need thermal reliefs. Learn from professionals - check their designs of hi-frequency boards. Often they provide gerber files of reference design PCB's. One of many examples attached

[cgroen]

Thermal reliefs are against thombstoning of tiny components or in favor of low cost inferior hand-soldering. As edge-mount SMT sockets are not prone of tombstoning (rofl), you do not need thermal reliefs. Learn from professionals - check their designs of hi-frequency boards. Often they provide gerber files of reference design PCB's. One of many examples attached

Im all for learning
Regarding the SMA, I have added a a copy of one of the lines, one set is with thermal relief to the SMA, the other is direct connect. This will demonstrate the difference if there is any.
On the components, in this case it is not an option as I need to be able to do easy replacement of networks (for experiments). I don't want to mess with hotair and heating from the back when doing that.

[thinkfat]

The Microstrip calculator at Chemandy gives 49.6 Ohm for the JLC7628 stackup using \$\epsilon_r=4.5\$.

PS: the \$\epsilon_r\$ of the solder mask is not relevant for microstrip, there's no field above the trace to interact with it.

Sorry, I edited the post while you wrote your reply. You can forget about the solder mask for microstrip. For CPW it might have some influence. But I don't know how much. Surely the effective \$\epsilon_r\$ will not be 3.8.

Are you sure ? According to this it has: https://www.multi-circuit-boards.eu/en/pcb-design-aid/impedance-calculation.html

Well, there's your next testcase But seriously, I don't see why the effective \$\epsilon_r\$ would be the one of the coating all of a sudden. The electric field forms between the transmission line and whatever contributes to the return path. So there will be some influence of the solder mask. But the majority of the field is between the trace and the reference plane.

[cgroen]

Well, there's your next testcase But seriously, I don't see why the effective \$\epsilon_r\$ would be the one of the coating all of a sudden. The electric field forms between the transmission line and whatever contributes to the return path. So there will be some influence of the solder mask. But the majority of the field is between the trace and the reference plane.

Good idea
Now there are 3 equal sets, one with direct connection to SMA, one with thermal relief (both with soldermask) and the last without soldermask (and with thermal relief)
Luckily I have ordered a bunch of SMA

[ogden]

Im all for learning
Regarding the SMA, I have added a a copy of one of the lines, one set is with thermal relief to the SMA, the other is direct connect. This will demonstrate the difference if there is any.

Glad to see right attitude Tests and hints are how we learn. You shall see impact of "thermal reliefs" at higher frequencies - because wires/traces are inductors, even short ones.

[thm_w]

Thermal reliefs are against tombstoning of tiny components or in favor of low cost inferior hand-soldering. As edge-mount SMT sockets are not prone of tombstoning (rofl), you do not need thermal reliefs. Learn from professionals - check their designs of hi-frequency boards. Often they provide gerber files of reference design PCB's. One of many examples attached

Whats with the wide pad on the SMA center pin? Most designs I see use the width of the pin.

[ogden]

Thermal reliefs are against tombstoning of tiny components or in favor of low cost inferior hand-soldering. As edge-mount SMT sockets are not prone of tombstoning (rofl), you do not need thermal reliefs. Learn from professionals - check their designs of hi-frequency boards. Often they provide gerber files of reference design PCB's. One of many examples attached

Whats with the wide pad on the SMA center pin? Most designs I see use the width of the pin.

Impedance matching. At that exact point.
[edit] BTW - What designs you are referring to?
[side note] ZLNE3 is around 15k$ @tequipment.net

[thm_w]

Impedance matching. At that exact point.
[edit] BTW - What designs you are referring to?
[side note] ZLNE3 is around 15k$ @tequipment.net

Just a google search for SMA layout.
Finds various eval PCBs, etc.
https://ez.analog.com/rf/f/q-a/71227/a-question-about-sma-connector-to-pcb
https://hackaday.io/project/162998-the-rise-and-fall-of-pulses/log/162831-pcb-trace-impedance-revisited

edit: there is also taper like this: https://www.sigcon.com/Pubs/edn/TaperedTransitions.htm

[thinkfat]

I was wondering about the SMA center pad, too. It's clearly too wide and will impact S11, unless maybe you remove the inner layers and leave only the bottom groundplane. But then you'll have a discontinuity at the point where your wave hits the transmission line structure and you need to carefully create a transition area. It's better to keep the geometry as constant as possible.

[cgroen]

.
Just a google search for SMA layout.
Finds various eval PCBs, etc.
https://ez.analog.com/rf/f/q-a/71227/a-question-about-sma-connector-to-pcb
https://hackaday.io/project/162998-the-rise-and-fall-of-pulses/log/162831-pcb-trace-impedance-revisited

edit: there is also taper like this: https://www.sigcon.com/Pubs/edn/TaperedTransitions.htm

Thanks for the links! The hackaday page mentions 3 Ohms difference with soldermask/no soldermask, but he also mentions that this is probably because its a 2 layer board (larger distance between the trace and ground). Will be interesting to see the impact on my 4 layer board.

I was wondering about the SMA center pad, too. It's clearly too wide and will impact S11, unless maybe you remove the inner layers and leave only the bottom groundplane. But then you'll have a discontinuity at the point where your wave hits the transmission line structure and you need to carefully create a transition area. It's better to keep the geometry as constant as possible.

According to Molex for the connector I use from them, the center pad should be 2.29 mm (which continues out in a trace that is 2.62 mm). The center pin is 0.76 mm in diameter. I have made the pad in my footprint 1 mm wide, maybe I should narrow that down even more ?

Drawing: https://www.molex.com/pdm_docs/sd/732511150_sd.pdf

[ogden]

I was wondering about the SMA center pad, too. It's clearly too wide and will impact S11, unless maybe you remove the inner layers and leave only the bottom groundplane. But then you'll have a discontinuity at the point where your wave hits the transmission line structure and you need to carefully create a transition area. It's better to keep the geometry as constant as possible.

You are correct that it will impact S11, but in a good way. That "pad" is for impedance matching between "stripline-compatible" generic low cost SMA and Grounded Coplanar Wave Guides (GCWG). No offense, but accusing Hittite / Analog Devices of incorrect microwave reference design PCB is laughable. If you want to connect edge-mount connector into GCWG directly - use proper connector then! For microwave development work, test boards I would suggest Amphenol 2921-61674 because they are reusable (no solder). For final products one can use something like Johnson 142-0761-871. [edit] Similar to johnson connector used in the pic attached.

[nctnico]

Again: Use Sonnet to check your trace geometries!

I tried, installed it, looked at the complexity of it, and removed it again
I "just" need to calculate the impedance of simple tracks, not take over the world (with an 824 MByte application).....

It is not that simple. I also see some components on your board. With Sonnect you can simulate how grounding vias affect the signal and this isn't straightforward. IMHO the way you are going is trying to hit a piñata in the dark; making an RF board without insight in how it actually behaves is just a waste of money.

[cgroen]

Again: Use Sonnet to check your trace geometries!

I tried, installed it, looked at the complexity of it, and removed it again
I "just" need to calculate the impedance of simple tracks, not take over the world (with an 824 MByte application).....

It is not that simple. I also see some components on your board. With Sonnect you can simulate how grounding vias affect the signal and this isn't straightforward. IMHO the way you are going is trying to hit a piñata in the dark; making an RF board without insight in how it actually behaves is just a waste of money.

I'm not after the last "0.1 dB" in this. I'm also not "making an RF board", I'm simply trying to (within a ballpark) to figure out approx what it takes to make a "close enough" to 50 Ohm line on a JLCPCB board. The ones I have tried so far, was way out from anything close to 50 Ohm. This "50 Ohm" line will eventually go into a large design where this is just a single trace in a complex board (that has nothing to do with RF other than this single line).
I know that if I want to go "full blown", that stuff like Sonnect is needed, but I have a hope that less than that can get me "close enough"

The components on board is purely for experimentation (with the VNA), besides the 50 ohm termination resistors, the rest is just "for fun"

[nctnico]

Again: Use Sonnet to check your trace geometries!

I tried, installed it, looked at the complexity of it, and removed it again
I "just" need to calculate the impedance of simple tracks, not take over the world (with an 824 MByte application).....

It is not that simple. I also see some components on your board. With Sonnect you can simulate how grounding vias affect the signal and this isn't straightforward. IMHO the way you are going is trying to hit a piñata in the dark; making an RF board without insight in how it actually behaves is just a waste of money.

I'm not after the last "0.1 dB" in this. I'm also not "making an RF board", I'm simply trying to (within a ballpark) to figure out approx what it takes to make a "close enough" to 50 Ohm line on a JLCPCB board. The ones I have tried so far, was way out from anything close to 50 Ohm. This "50 Ohm" line will eventually go into a large design where this is just a single trace in a complex board (that has nothing to do with RF other than this single line).
I know that if I want to go "full blown", that stuff like Sonnect is needed, but I have a hope that less than that can get me "close enough"

You are making an RF board. There is no other way to put it (even if it is for high speed 'digital'; high speed digital design is nothing else than RF design). And it is not about getting to 0.1 dB accuracy because that is impossible due to component and manufacturing tolerances. Using the Sonnet software gives you insight in how RF signals interact with your board design at a level you'll never be able to achieve through using test equipment. It can show current densities in your board layout for example. Yes, there is a learning curve but IMHO it is time well spend.

[thinkfat]

Again: Use Sonnet to check your trace geometries!

Without access to Sonnet, I tried my hands on openEMS. I use KiCADs "HyperLynx" export feature to get a PCB into openEMS, but it's tough going. openEMS is used through Matlab modules and getting a simulation going involves writing a matlab program, manually adding (in code) excitation, ports, components and a mesh. Although the mesh can be automatically generated, it is frequently not optimal and leads to long simulation times and garbage output.

I hope Sonnet doesn't have an as steep learning curve, but I can imagine you'd have some work ahead to getting it going. But I'm not getting what is the gain here. The goal for this thread is to understand the manufacturing process of JLCPCB and for this purpose it should be enough to poke some numbers into a pcb calculator, get the boards made and then measure them.