Electronics > PCB/EDA/CAD

Measurement of different PCB trace width with R&S ZLNE-3 VNA / JLCPCB

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nctnico:

--- Quote from: thinkfat on January 10, 2022, 08:34:26 am ---
--- Quote from: nctnico on January 07, 2022, 02:57:54 pm ---Again: Use Sonnet to check your trace geometries!

--- End quote ---

Without access to Sonnet, I tried my hands on openEMS. I use KiCADs "HyperLynx" export feature to get a PCB into openEMS, but it's tough going. openEMS is used through Matlab modules and getting a simulation going involves writing a matlab program, manually adding (in code) excitation, ports, components and a mesh. Although the mesh can be automatically generated, it is frequently not optimal and leads to long simulation times and garbage output.

I hope Sonnet doesn't have an as steep learning curve, but I can imagine you'd have some work ahead to getting it going.


--- End quote ---
There is a free version for Sonnet called Sonnet Lite. You have to ask for a license but this is not a difficult process.  However, I would not recommend to use Sonnet for simulation entire PCBs; it is too slow and needs too much memory for that. AFAIK Sonnet is aimed at simulating small chunks. Think about resonators, trace discontinuities, microstrip filters, etc. What goes for 2cm of microstrip also goes for 20cm of microstrip.


--- Quote ---But I'm not getting what is the gain here. The goal for this thread is to understand the manufacturing process of JLCPCB and for this purpose it should be enough to poke some numbers into a pcb calculator, get the boards made and then measure them.

--- End quote ---
As the OP already noted: every calculator gives a different answer, the calculator doesn't take the actual PCB geometries into account and there can be large errors in case the geometries are far from what is ideal for the calculator. In the end the calculators are using formulas derived from empirical data.

OTOH Sonnet will give the right answer based on the actual geometry you provide. In Sonnet you define a PCB stackup, the surroundings and PCB layers. From there you can run a simulation. The free version has limits where it comes to memory use (which in turn limits size versus granularity).

ogden:
Video about trace impedances: https://youtu.be/U60y4JC0Wxs?t=1

cgroen:
Thanks for all the input and discussions so far, was very helpful and informative!

I have just ordered the board below, I'll get back once it arrives and I have it assembled. I selected to get it with HASL surface instead of ENIG as JLCPCB does not do ENIG boards before feb 8 again (CNY)
(I have ordered 5 pcs, if any of you wants one of the 4 "leftovers" you can have it for free, except for the shipping from me to you ;) Only caveat is that you publish whatever you find out here in this thread  ^-^)

Gerhard_dk4xp:
Everybody seems to do just this. We just had a discussion about solder mask effects
on usenet sci.electronics.design which is mirrored by google groups.
JL found out that the solder mask has no visible effect on the TDR (other manufacturer).
JohnL also said that the SMAs with the thick inner conductor have 100 Ohms in air
already without any board attached. I believe that.

I also tested the JLCPCB process with an Agilent 54754A TDR.
The 11.5 mil trace  seems to be absolutely correct. I drew it as 12 mil
in Altium, that makes it maybe a tad lower impedance when the
50 Ohm line in the 54754A is taken as a reference.

My SMA launchers were a disaster. I took the ones for a 2 layer board
and the center conductor was much too large.
The next board is on its way, with GND cut outs in the SMAs. I have no
idea where. Shipment tracking says it was in in Leipzig, Germany and
somehow it has jumped back to Hong Kong???
The board is a 15 GHz LMX2594 synthesizer to be shown in DUBUS 1/22
so I can't be too verbose bc I have promised the ius primae noctis to
Dubus , but methinks they'll tolerate a picture for a discussion.

Cheers, Gerhard

rfclown:
Notice that Gerhard_dk4xp's board does not have ground on the top layer near the trace. This is microstrip. With ground on either side you have a grounded coplaner waveguide which has more capacitance per unit length than microstrip and therefore lower impedance (Zo=SQRT(L/C)) given the same dimensions (width, height). Solder mask has minimal effect. Conductor thickness has more effect than mask, which is why you need to calculate with the finished thickness (after plating). When doing boards with a thin dielectic on the top layer which makes for a thin 50 ohm line, if the pad for the SMA edge launch pin needs to be wider, you can eliminate ground directly under the pin pad to increase the dielectric thickness. I'll calculate what the pin pad width will be (to get 50 ohms) if the ground is on layer 3, or 4, or 5... I'll chose a ground reference layer for the pin pad that gives me an appropriate width for soldering the SMA pin.

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