Measurement of different PCB trace width with R&S ZLNE-3 VNA / JLCPCB

[cgroen]

As my Christmas present to myself this year was a brand new R&S ZNLE-3 VNA and a ZN-Z150 calibrator, I thought it would be nice (finally) to measure the impedance of different trace width from JLCPCB.
According to JLCPCB's "impedance calculator" for their JLC7628 stackup, a trace of 11.55 mil should give 50 Ohms.
I made a small 4 layer 1.6mm thick PCB with 4 different traces on it, 8, 10, 12 and 14 mil wide. Each trace was terminated with a 50.3 Ohm resistor (0402, 1%, using thermal relief on GND). All 4 layers had ground pour on them and lots of VIA's.
The clearance around the tracks where 3 times the width of the tracks.
SMA connectors used was Molex: https://www.molex.com/molex/products/part-detail/rf_coax_connectors/0732511150
Cable used was a Minicircuits SMA cable.

As I have not yet received the calibrator for the VNA, I used what I had laying around (open, short and 50 Ohm) of decent quality (I hope..).

Below is the result from 1 MHz to 3 GHz of the 4 different tracks. Now, I'm no RF expert (at all!), so I might have failed in the measurements/setups, if you spot anything strange, please let me know!
It seems that the orange track (10 mil trace) is the one that is least "bad".
Maybe I have had too high expectations, or even more possible, I did something wrong, but I would have guessed that the return loss would have been better ?

EDIT: Smith chart included also

[cgroen]

Zoomed in on the smith chart:

[thinkfat]

To me it looks like the 10mil trace has the closest match. It has the least wiggles in the logmag graph and also on the smith chart is somewhat straight. However, it is quite obvious from the smith chart that the impedance is mostly inductive capacitive and also quite far from 50 Ohms other than at the very start of the frequency range.

Unfortunately, my RF experience is also quite limited so I don't quite know what this is due to. But it seems really quite odd, the S11 logmag graph should stay below at least -20dB reflected power for most of the range, but instead it rises quickly to be above -10dB. That doesn't look good. I suspect a mistake in your layout somewhere, or in the calibration of the VNA. Could you provide the Gerber files for all 4 layers?

I would, anyway, suggest to drop all the thermal reliefs in the GND pads and make the signal pads for the SMA connectors a lot thinner. Also, put ground vias directly under the connector flanges, not somewhere outside. This all adds inductance.

It would also be quite interesting to see what difference a much wider clearance between the signal trace and the ground fill on the top layer would make and if you were to make another set of boards, have one 10mil trace with SMA connectors on both ends so that you can measure S21 as well.

Putting SMA connectors on both ends would have been the better test setup anyway, IMHO. But I hope someone with more RF experience will take a look as well.

[cgroen]

To me it looks like the 10mil trace has the closest match. It has the least wiggles in the logmag graph and also on the smith chart is somewhat straight. However, it is quite obvious from the smith chart that the impedance is mostly inductive and also quite far from 50 Ohms other than at the very start of the frequency range.

Unfortunately, my RF experience is also quite limited so I don't quite know what this is due to. But it seems really quite odd, the S11 logmag graph should stay below at least -20dB reflected power for most of the range, but instead it rises quickly to be above -10dB. That doesn't look good. I suspect a mistake in your layout somewhere, or in the calibration of the VNA. Could you provide the Gerber files for all 4 layers?

I would, anyway, suggest to drop all the thermal reliefs in the GND pads and make the signal pads for the SMA connectors a lot thinner. Also, put ground vias directly under the connector flanges, not somewhere outside. This all adds inductance.

It would also be quite interesting to see what difference a much wider clearance between the signal trace and the ground fill on the top layer would make and if you were to make another set of boards, have one 10mil trace with SMA connectors on both ends so that you can measure S21 as well.

Putting SMA connectors on both ends would have been the better test setup anyway, IMHO. But I hope someone with more RF experience will take a look as well.

Thanks for input! To be honest, the connectors I used was not what the PCB was laid out for, so it ended up being a compromise...
I have attached the gerbers for the board. I have since changed the layout to the right connector and added a few more things to the board (some experiments with matching circuits etc). This one has also a SMA on one of the "channels", maybe it is better as you write to do this on all of them!

[thinkfat]

I have probably misread the smith chart a bit, the impedance is not inductive, it is capacitive. In that case, I guess the problem is that the ground fills are too close to the signal traces.

To give some reference, I've attached some pictures of a resistive power splitter I made for some experiment. The PCB was done not with a specific impedance controlled stack-up, I just calculated some trace widths for standard 1.6mm FR4 PCB. The PCB was manufactured by JLCPCB, though. As you can see, the reflected power is better than -20dB up to 1GHz (I didn't check higher frequency because the target frequency was below 100MHz anyway). Impedance is close to 50 Ohm across the span, slightly inductive for the most part, turning capacitive towards the end of the range. This is how I expected your smith chart to look like, too.

BTW, what is the frequency/div in your plot? I somehow cannot see that from the screenshots.

[cgroen]

Thanks,
the span is 3 GHz (from 1 MHz to 3 GHz) with 10 divisions, so 300 MHz per division (almost).
I have made some adjustments to the testboard, perhaps I should even make some with more spacing. So far this is it:

(I also made a "cheat sheet" for Smith chart as it is almost half a century ago I looked at that, attached here also)

[m98]

The calculator you used was for a microstrip, not a coplanar waveguide with ground

[thinkfat]

I would be much, much more generous with ground clearance, also around the SMA center pad. You don't need any ground fill adjacent to the signal trace, on the contrary. This is not a CPW or GCPW, you calculated the trace width for microstrip.

PS: quick calculation for a GCPW with 10mil trace and 30mil space gives around 62 Ohms for the JLC7628 stackup.

PPS: I guess your VNA can do TDR as well? That could be quite interesting. What I'm guessing you'd see is a jump where the SMA center pin connects to the trace and another one where the microstrip trace ends in the termination resistor.

[cgroen]

The calculator you used was for a microstrip, not a coplanar waveguide with ground

I would be much, much more generous with ground clearance, also around the SMA center pad. You don't need any ground fill adjacent to the signal trace, on the contrary. This is not a CPW or GCPW, you calculated the trace width for microstrip.

PS: quick calculation for a GCPW with 10mil trace and 30mil space gives around 62 Ohms for the JLC7628 stackup.

PPS: I guess your VNA can do TDR as well? That could be quite interesting. What I'm guessing you'd see is a jump where the SMA center pin connects to the trace and another one where the microstrip trace ends in the termination resistor.

Ahh yes, thanks! I didn't pay enough attention to the type of trace 
If I use Er=4.6, thickness 0.2 mm (as per JLCPCB stackup) a track width of 0.36 mm and a gap (on both sides) of 0.25 mm should arrive at 49.99 Ohm. Does that sound reasonable ?
(thinkfat, I arrive also at 62 Ohm with the numbers used)
Regarding TDR, thats unfortunately an (very expensive!) software option for the VNA....

[thinkfat]

The calculator you used was for a microstrip, not a coplanar waveguide with ground

I would be much, much more generous with ground clearance, also around the SMA center pad. You don't need any ground fill adjacent to the signal trace, on the contrary. This is not a CPW or GCPW, you calculated the trace width for microstrip.

PS: quick calculation for a GCPW with 10mil trace and 30mil space gives around 62 Ohms for the JLC7628 stackup.

PPS: I guess your VNA can do TDR as well? That could be quite interesting. What I'm guessing you'd see is a jump where the SMA center pin connects to the trace and another one where the microstrip trace ends in the termination resistor.

Ahh yes, thanks! I didn't pay enough attention to the type of trace 
If I use Er=4.6, thickness 0.2 mm (as per JLCPCB stackup) a track width of 0.36 mm and a gap (on both sides) of 0.25 mm should arrive at 49.99 Ohm. Does that sound reasonable ?
(thinkfat, I arrive also at 62 Ohm with the numbers used)

Yes, that sounds about right. Maybe you can add that to your test PCB as well. I'm not so familiar with coplanar waveguide structures, I've only read about them. It seems they're a bit fiddly to handle on a PCB because the mode of conduction has a significant electric field "above" the PCB. I've only ever done short microstrip lines at 1 GHz or so, that's where my experience ends. But I've always given plenty of clearance to the top ground fill.

[Leo Bodnar]

I am interested in comparative practicality and accuracy of VNA vs TDR usage for PCB stackup verifications. 
I have used TDR for this but, perhaps, VNA is more modern and portable method?
With TDR it's very easy to see past the launch (SMA or pad) point.  How do you de-embed launch and termination using VNA?
Leo

[cgroen]

.
Yes, that sounds about right. Maybe you can add that to your test PCB as well. I'm not so familiar with coplanar waveguide structures, I've only read about them. It seems they're a bit fiddly to handle on a PCB because the mode of conduction has a significant electric field "above" the PCB. I've only ever done short microstrip lines at 1 GHz or so, that's where my experience ends. But I've always given plenty of clearance to the top ground fill.

I'm adding a few different layouts to the testboard, I will report back here once I get the new boards.

I am interested in comparative practicality and accuracy of VNA vs TDR usage for PCB stackup verifications. 
I have used TDR for this but, perhaps, VNA is more modern and portable method?
With TDR it's very easy to see past the launch (SMA or pad) point.  How do you de-embed launch and termination using VNA?
Leo

I guess you should be able to make a "back to back" PCB with just the connectors (eliminating the trace) and use that. The ZNLE-3 I have has a lot of settings/menus that I have not touched yet, but "de-embedding" etc is mentioned several times on the instrument (and in R&S youtube videos).
Still a lot to learn for me 

[Leo Bodnar]

This is what I have played with - the trace was just an open end trace on PCB panel tooling strip.
I am using Agilent N1020A probe to launch the pulse.

I expect modern VNA to be able to perform inversion solution and output time-domain TDR plot.  Or is it not that simple?

Leo

[cgroen]

This is what I have played with - the trace was just an open end trace on PCB panel tooling strip.
I am using Agilent N1020A probe to launch the pulse.

I expect modern VNA to be able to perform inversion solution and output time-domain TDR plot.  Or is it not that simple?

Leo

Yes, I think they are capable of that, however in the case of my instrument, TDR has an added cost of around €5000 if I remember correctly (wonder if there are any key generators for that  )

[cgroen]

This is what I intend to do next, if any of you guys have more input / things to add, just say so !
I have made the center pad for the SMA connector smaller than recommended by Molex, they just cover the center pin now.
(numbers in paranthises is calculated impedance)

[thinkfat]

This is what I have played with - the trace was just an open end trace on PCB panel tooling strip.
I am using Agilent N1020A probe to launch the pulse.

I expect modern VNA to be able to perform inversion solution and output time-domain TDR plot.  Or is it not that simple?

At least my NanoVNA V2 can do it. I have not much experience with it, though, I've only played around with it.

[thinkfat]

This is what I intend to do next, if any of you guys have more input / things to add, just say so !
I have made the center pad for the SMA connector smaller than recommended by Molex, they just cover the center pin now.
(numbers in paranthises is calculated impedance)

If you'd add at least one actual microstrip transmission line, say, 11mil, with a couple millimeters clearance to the top ground fill, that'd be awesome.

[cgroen]

This is what I intend to do next, if any of you guys have more input / things to add, just say so !
I have made the center pad for the SMA connector smaller than recommended by Molex, they just cover the center pin now.
(numbers in paranthises is calculated impedance)

If you'd add at least one actual microstrip transmission line, say, 11mil, with a couple millimeters clearance to the top ground fill, that'd be awesome.

Absolutely:
According to calculators, this will result in 64 Ohm? The trace needs (with 2 mm space on each side) to be 0.42 mm to be 50.5 Ohm)
But, when looking at the impedance calculator at JLCPCB, a trace of 11.55 mil should give 50 Ohm, so maybe this is a good test.

[gf]

I expect modern VNA to be able to perform inversion solution and output time-domain TDR plot.  Or is it not that simple?

Basically it is an IFFT. For lowpass mode (which gives the impulse response of S11 or S21 in the time domain) the measured frequency points must be evenly spaced, though, from 0...fmax. This may require extrapolation down to DC if the VNA cannot measure so low frequencies. After adding negative frequencies (with conjugate complex values of the positive ones) IFFT is calculated, whose result is a real-valued signal then, in the time domain. Usually also a window function is applied to the frequency domain data before IFFT to avoid ringing/Gibbs artifacts, but OTOH this smooths the resulting impule respose, so it is a compromise. The step response is the integral (or accumulated sum in the discrete world) of the impulse respose then. The impulse/step response of S11 can also be converted to other units, for instance an impedance profile over time (distance) can be plotted.

A 0...3GHz sweep leads to a time resolution of 6GSa/s, but the smeared pulse width (or rise time) is rather a couple of samples, depending on the selected window function. If a better resolution than a few centimeters is needed, then 3GHz is not sufficient, but a higher frequency range needs to be swept.

At least my NanoVNA V2 can do it. I have not much experience with it, though, I've only played around with it.

It can. Unfortunately it renounces 50% of the possible resolution in lowpass mode (FFT size too snall), and the extralolation is IMO not implemented correctly; fortunately the latter seems to have not too much effect on the result. If the pulse/step starts partly outside the screen, then adding EDELAY of say -1ns helps I order to shift the pulse horizontally.

[nctnico]

If you want to be sure about PCB trace geometry, use a field solver (like Sonnet Lite). PCB trace impedance calculators are usually wrong; especially with trace impedances other than 50 Ohm.

[thinkfat]

If you want to be sure about PCB trace geometry, use a field solver (like Sonnet Lite). PCB trace impedance calculators are usually wrong; especially with trace impedances other than 50 Ohm.

Theoretically. But I don't think JLCPCBs process is well enough controlled to model the PCBs for a field solver with better precision than a beer-soaked-coaster calculation would yield.

[nctnico]

If you want to be sure about PCB trace geometry, use a field solver (like Sonnet Lite). PCB trace impedance calculators are usually wrong; especially with trace impedances other than 50 Ohm.

Theoretically. But I don't think JLCPCBs process is well enough controlled to model the PCBs for a field solver with better precision than a beer-soaked-coaster calculation would yield.

That goes for any PCB manufacturer. But you can mitigate that by choosing the stackup in a way that the trace width is large compared to the etching tolerances. That way you can achieve very accurate results. But that is not really my point; the online calculators just aren't good enough.

[cgroen]

According to JLCPCB, a 50 Ohm trace should be 11.55 mil wide. If I punch the numbers into a calculator, this should give 63 Ohm (at Er=4.6).
Something is clearly not right ?!

So far, my next testboard looks like this (ideas more than welcome, I will be ordering in a couple of days)

[nctnico]

Again: Use Sonnet to check your trace geometries!

[2N3055]

11,5 mils trace and spacing on FR4 (at Er=4.6) and 1,5mm board gives me 49,6 Ohms, for a coplanar waveguide

0.29 mm trace/spacing on 1.5 mm gives 49,9 Ohm

That is in AppCAD.

[cgroen]

Again: Use Sonnet to check your trace geometries!

I tried, installed it, looked at the complexity of it, and removed it again
I "just" need to calculate the impedance of simple tracks, not take over the world (with an 824 MByte application).....

[cgroen]

11,5 mils trace and spacing on FR4 (at Er=4.6) and 1,5mm board gives me 49,6 Ohms, for a coplanar waveguide

That is in AppCAD.

It's a 4 layer, 0.2mm to L2 (GND) in my case (JLC7628 stackup).
According to JLCPCB (https://cart.jlcpcb.com/impedance?_ga=2.33326718.1500801373.1641198313-6221190.1604429483) The Er is 3.8 for a coated track if I understand correctly (and 4.6 for bare copper), or am I wrong ?

[thinkfat]

11,5 mils trace and spacing on FR4 (at Er=4.6) and 1,5mm board gives me 49,6 Ohms, for a coplanar waveguide

That is in AppCAD.

It's a 4 layer, 0.2mm to L2 (GND) in my case (JLC7628 stackup).
According to JLCPCB (https://cart.jlcpcb.com/impedance?_ga=2.33326718.1500801373.1641198313-6221190.1604429483) The Er is 3.8 for a coated track if I understand correctly (and 4.6 for bare copper), or am I wrong ?

The prepreg height (H1) is only 7.1mil in case of conductor on the outside, not 0.2mm. If I use that and the specified \$\epsilon_r = 4.5\$ I get roughly 51 Ohm for a 11.55mil microstrip line. Remember that the impedance calculator on the JLCPCB website is for microstrip, not for CPW.

[cgroen]

11,5 mils trace and spacing on FR4 (at Er=4.6) and 1,5mm board gives me 49,6 Ohms, for a coplanar waveguide

That is in AppCAD.

It's a 4 layer, 0.2mm to L2 (GND) in my case (JLC7628 stackup).
According to JLCPCB (https://cart.jlcpcb.com/impedance?_ga=2.33326718.1500801373.1641198313-6221190.1604429483) The Er is 3.8 for a coated track if I understand correctly (and 4.6 for bare copper), or am I wrong ?

The prepreg height (H1) is only 7.1mil in case of conductor on the outside, not 0.2mm. If I use that and the specified \$\epsilon_r = 4.5\$ I get roughly 51 Ohm for a 11.55mil microstrip line. Remember that the impedance calculator on the JLCPCB website is for microstrip, not for CPW.

According to their spec, the prepreg (for 7628) is 0.2 mm
Their Er is 4.6, and (if I understand correctly) it is 3.8 for "covered" tracks (solder resist)

Edit: Ah, I see where you get the 7.1 mil from, wonder which one is correct ?

[2N3055]

11,5 mils trace and spacing on FR4 (at Er=4.6) and 1,5mm board gives me 49,6 Ohms, for a coplanar waveguide

That is in AppCAD.

It's a 4 layer, 0.2mm to L2 (GND) in my case (JLC7628 stackup).
According to JLCPCB (https://cart.jlcpcb.com/impedance?_ga=2.33326718.1500801373.1641198313-6221190.1604429483) The Er is 3.8 for a coated track if I understand correctly (and 4.6 for bare copper), or am I wrong ?

Well what I calculated is for a standard 2 layer board... numbers are to close to be coincidence.
Is their calculator calculating for wrong stackup?

[cgroen]

11,5 mils trace and spacing on FR4 (at Er=4.6) and 1,5mm board gives me 49,6 Ohms, for a coplanar waveguide

That is in AppCAD.

It's a 4 layer, 0.2mm to L2 (GND) in my case (JLC7628 stackup).
According to JLCPCB (https://cart.jlcpcb.com/impedance?_ga=2.33326718.1500801373.1641198313-6221190.1604429483) The Er is 3.8 for a coated track if I understand correctly (and 4.6 for bare copper), or am I wrong ?

Well what I calculated is for a standard 2 layer board... numbers are to close to be coincidence.
Is their calculator calculating for wrong stackup?

I'm not using the calculator at JLC, I have tried a number of different (that all agree), one of them is Saturn PCB.
Saturn PCB seems to be on line with (microstrip): https://chemandy.com/calculators/microstrip-transmission-line-calculator-ipc2141.htm
And with this (CPW): https://chemandy.com/calculators/coplanar-waveguide-with-ground-calculator.htm

[thinkfat]

The Microstrip calculator at Chemandy gives 49.6 Ohm for the JLC7628 stackup using \$\epsilon_r=4.5\$.

PS: the \$\epsilon_r\$ of the solder mask is not relevant for microstrip, there's no field above the trace to interact with it.

[cgroen]

The Microstrip calculator at Chemandy gives 49.6 Ohm for the JLC7628 stackup using \$\epsilon_r=4.5\$.

Yes. But, is it in fact Er 4.5 or 3.8 to be used if solder resist on the track (I would guess 3.

[thinkfat]

The Microstrip calculator at Chemandy gives 49.6 Ohm for the JLC7628 stackup using \$\epsilon_r=4.5\$.

PS: the \$\epsilon_r\$ of the solder mask is not relevant for microstrip, there's no field above the trace to interact with it.

Sorry, I edited the post while you wrote your reply. You can forget about the solder mask for microstrip. For CPW it might have some influence. But I don't know how much. Surely the effective \$\epsilon_r\$ will not be 3.8.

[cgroen]

The Microstrip calculator at Chemandy gives 49.6 Ohm for the JLC7628 stackup using \$\epsilon_r=4.5\$.

PS: the \$\epsilon_r\$ of the solder mask is not relevant for microstrip, there's no field above the trace to interact with it.

Sorry, I edited the post while you wrote your reply. You can forget about the solder mask for microstrip. For CPW it might have some influence. But I don't know how much. Surely the effective \$\epsilon_r\$ will not be 3.8.

Are you sure ? According to this it has: https://www.multi-circuit-boards.eu/en/pcb-design-aid/impedance-calculation.html

[ogden]

Thermal reliefs are against thombstoning of tiny components or in favor of low cost inferior hand-soldering. As edge-mount SMT sockets are not prone of tombstoning (rofl), you do not need thermal reliefs. Learn from professionals - check their designs of hi-frequency boards. Often they provide gerber files of reference design PCB's. One of many examples attached

[cgroen]

Thermal reliefs are against thombstoning of tiny components or in favor of low cost inferior hand-soldering. As edge-mount SMT sockets are not prone of tombstoning (rofl), you do not need thermal reliefs. Learn from professionals - check their designs of hi-frequency boards. Often they provide gerber files of reference design PCB's. One of many examples attached

Im all for learning
Regarding the SMA, I have added a a copy of one of the lines, one set is with thermal relief to the SMA, the other is direct connect. This will demonstrate the difference if there is any.
On the components, in this case it is not an option as I need to be able to do easy replacement of networks (for experiments). I don't want to mess with hotair and heating from the back when doing that.

[thinkfat]

The Microstrip calculator at Chemandy gives 49.6 Ohm for the JLC7628 stackup using \$\epsilon_r=4.5\$.

PS: the \$\epsilon_r\$ of the solder mask is not relevant for microstrip, there's no field above the trace to interact with it.

Sorry, I edited the post while you wrote your reply. You can forget about the solder mask for microstrip. For CPW it might have some influence. But I don't know how much. Surely the effective \$\epsilon_r\$ will not be 3.8.

Are you sure ? According to this it has: https://www.multi-circuit-boards.eu/en/pcb-design-aid/impedance-calculation.html

Well, there's your next testcase But seriously, I don't see why the effective \$\epsilon_r\$ would be the one of the coating all of a sudden. The electric field forms between the transmission line and whatever contributes to the return path. So there will be some influence of the solder mask. But the majority of the field is between the trace and the reference plane.

[cgroen]

Well, there's your next testcase But seriously, I don't see why the effective \$\epsilon_r\$ would be the one of the coating all of a sudden. The electric field forms between the transmission line and whatever contributes to the return path. So there will be some influence of the solder mask. But the majority of the field is between the trace and the reference plane.

Good idea
Now there are 3 equal sets, one with direct connection to SMA, one with thermal relief (both with soldermask) and the last without soldermask (and with thermal relief)
Luckily I have ordered a bunch of SMA

[ogden]

Im all for learning
Regarding the SMA, I have added a a copy of one of the lines, one set is with thermal relief to the SMA, the other is direct connect. This will demonstrate the difference if there is any.

Glad to see right attitude Tests and hints are how we learn. You shall see impact of "thermal reliefs" at higher frequencies - because wires/traces are inductors, even short ones.

[thm_w]

Thermal reliefs are against tombstoning of tiny components or in favor of low cost inferior hand-soldering. As edge-mount SMT sockets are not prone of tombstoning (rofl), you do not need thermal reliefs. Learn from professionals - check their designs of hi-frequency boards. Often they provide gerber files of reference design PCB's. One of many examples attached

Whats with the wide pad on the SMA center pin? Most designs I see use the width of the pin.

[ogden]

Thermal reliefs are against tombstoning of tiny components or in favor of low cost inferior hand-soldering. As edge-mount SMT sockets are not prone of tombstoning (rofl), you do not need thermal reliefs. Learn from professionals - check their designs of hi-frequency boards. Often they provide gerber files of reference design PCB's. One of many examples attached

Whats with the wide pad on the SMA center pin? Most designs I see use the width of the pin.

Impedance matching. At that exact point.
[edit] BTW - What designs you are referring to?
[side note] ZLNE3 is around 15k$ @tequipment.net

[thm_w]

Impedance matching. At that exact point.
[edit] BTW - What designs you are referring to?
[side note] ZLNE3 is around 15k$ @tequipment.net

Just a google search for SMA layout.
Finds various eval PCBs, etc.
https://ez.analog.com/rf/f/q-a/71227/a-question-about-sma-connector-to-pcb
https://hackaday.io/project/162998-the-rise-and-fall-of-pulses/log/162831-pcb-trace-impedance-revisited

edit: there is also taper like this: https://www.sigcon.com/Pubs/edn/TaperedTransitions.htm

[thinkfat]

I was wondering about the SMA center pad, too. It's clearly too wide and will impact S11, unless maybe you remove the inner layers and leave only the bottom groundplane. But then you'll have a discontinuity at the point where your wave hits the transmission line structure and you need to carefully create a transition area. It's better to keep the geometry as constant as possible.

[cgroen]

.
Just a google search for SMA layout.
Finds various eval PCBs, etc.
https://ez.analog.com/rf/f/q-a/71227/a-question-about-sma-connector-to-pcb
https://hackaday.io/project/162998-the-rise-and-fall-of-pulses/log/162831-pcb-trace-impedance-revisited

edit: there is also taper like this: https://www.sigcon.com/Pubs/edn/TaperedTransitions.htm

Thanks for the links! The hackaday page mentions 3 Ohms difference with soldermask/no soldermask, but he also mentions that this is probably because its a 2 layer board (larger distance between the trace and ground). Will be interesting to see the impact on my 4 layer board.

I was wondering about the SMA center pad, too. It's clearly too wide and will impact S11, unless maybe you remove the inner layers and leave only the bottom groundplane. But then you'll have a discontinuity at the point where your wave hits the transmission line structure and you need to carefully create a transition area. It's better to keep the geometry as constant as possible.

According to Molex for the connector I use from them, the center pad should be 2.29 mm (which continues out in a trace that is 2.62 mm). The center pin is 0.76 mm in diameter. I have made the pad in my footprint 1 mm wide, maybe I should narrow that down even more ?

Drawing: https://www.molex.com/pdm_docs/sd/732511150_sd.pdf

[ogden]

I was wondering about the SMA center pad, too. It's clearly too wide and will impact S11, unless maybe you remove the inner layers and leave only the bottom groundplane. But then you'll have a discontinuity at the point where your wave hits the transmission line structure and you need to carefully create a transition area. It's better to keep the geometry as constant as possible.

You are correct that it will impact S11, but in a good way. That "pad" is for impedance matching between "stripline-compatible" generic low cost SMA and Grounded Coplanar Wave Guides (GCWG). No offense, but accusing Hittite / Analog Devices of incorrect microwave reference design PCB is laughable. If you want to connect edge-mount connector into GCWG directly - use proper connector then! For microwave development work, test boards I would suggest Amphenol 2921-61674 because they are reusable (no solder). For final products one can use something like Johnson 142-0761-871. [edit] Similar to johnson connector used in the pic attached.

[nctnico]

Again: Use Sonnet to check your trace geometries!

I tried, installed it, looked at the complexity of it, and removed it again
I "just" need to calculate the impedance of simple tracks, not take over the world (with an 824 MByte application).....

It is not that simple. I also see some components on your board. With Sonnect you can simulate how grounding vias affect the signal and this isn't straightforward. IMHO the way you are going is trying to hit a piñata in the dark; making an RF board without insight in how it actually behaves is just a waste of money.

[cgroen]

Again: Use Sonnet to check your trace geometries!

I tried, installed it, looked at the complexity of it, and removed it again
I "just" need to calculate the impedance of simple tracks, not take over the world (with an 824 MByte application).....

It is not that simple. I also see some components on your board. With Sonnect you can simulate how grounding vias affect the signal and this isn't straightforward. IMHO the way you are going is trying to hit a piñata in the dark; making an RF board without insight in how it actually behaves is just a waste of money.

I'm not after the last "0.1 dB" in this. I'm also not "making an RF board", I'm simply trying to (within a ballpark) to figure out approx what it takes to make a "close enough" to 50 Ohm line on a JLCPCB board. The ones I have tried so far, was way out from anything close to 50 Ohm. This "50 Ohm" line will eventually go into a large design where this is just a single trace in a complex board (that has nothing to do with RF other than this single line).
I know that if I want to go "full blown", that stuff like Sonnect is needed, but I have a hope that less than that can get me "close enough"

The components on board is purely for experimentation (with the VNA), besides the 50 ohm termination resistors, the rest is just "for fun"

[nctnico]

Again: Use Sonnet to check your trace geometries!

I tried, installed it, looked at the complexity of it, and removed it again
I "just" need to calculate the impedance of simple tracks, not take over the world (with an 824 MByte application).....

It is not that simple. I also see some components on your board. With Sonnect you can simulate how grounding vias affect the signal and this isn't straightforward. IMHO the way you are going is trying to hit a piñata in the dark; making an RF board without insight in how it actually behaves is just a waste of money.

I'm not after the last "0.1 dB" in this. I'm also not "making an RF board", I'm simply trying to (within a ballpark) to figure out approx what it takes to make a "close enough" to 50 Ohm line on a JLCPCB board. The ones I have tried so far, was way out from anything close to 50 Ohm. This "50 Ohm" line will eventually go into a large design where this is just a single trace in a complex board (that has nothing to do with RF other than this single line).
I know that if I want to go "full blown", that stuff like Sonnect is needed, but I have a hope that less than that can get me "close enough"

You are making an RF board. There is no other way to put it (even if it is for high speed 'digital'; high speed digital design is nothing else than RF design). And it is not about getting to 0.1 dB accuracy because that is impossible due to component and manufacturing tolerances. Using the Sonnet software gives you insight in how RF signals interact with your board design at a level you'll never be able to achieve through using test equipment. It can show current densities in your board layout for example. Yes, there is a learning curve but IMHO it is time well spend.

[thinkfat]

Again: Use Sonnet to check your trace geometries!

Without access to Sonnet, I tried my hands on openEMS. I use KiCADs "HyperLynx" export feature to get a PCB into openEMS, but it's tough going. openEMS is used through Matlab modules and getting a simulation going involves writing a matlab program, manually adding (in code) excitation, ports, components and a mesh. Although the mesh can be automatically generated, it is frequently not optimal and leads to long simulation times and garbage output.

I hope Sonnet doesn't have an as steep learning curve, but I can imagine you'd have some work ahead to getting it going. But I'm not getting what is the gain here. The goal for this thread is to understand the manufacturing process of JLCPCB and for this purpose it should be enough to poke some numbers into a pcb calculator, get the boards made and then measure them.

[nctnico]

Again: Use Sonnet to check your trace geometries!

Without access to Sonnet, I tried my hands on openEMS. I use KiCADs "HyperLynx" export feature to get a PCB into openEMS, but it's tough going. openEMS is used through Matlab modules and getting a simulation going involves writing a matlab program, manually adding (in code) excitation, ports, components and a mesh. Although the mesh can be automatically generated, it is frequently not optimal and leads to long simulation times and garbage output.

I hope Sonnet doesn't have an as steep learning curve, but I can imagine you'd have some work ahead to getting it going.

There is a free version for Sonnet called Sonnet Lite. You have to ask for a license but this is not a difficult process.  However, I would not recommend to use Sonnet for simulation entire PCBs; it is too slow and needs too much memory for that. AFAIK Sonnet is aimed at simulating small chunks. Think about resonators, trace discontinuities, microstrip filters, etc. What goes for 2cm of microstrip also goes for 20cm of microstrip.

But I'm not getting what is the gain here. The goal for this thread is to understand the manufacturing process of JLCPCB and for this purpose it should be enough to poke some numbers into a pcb calculator, get the boards made and then measure them.

As the OP already noted: every calculator gives a different answer, the calculator doesn't take the actual PCB geometries into account and there can be large errors in case the geometries are far from what is ideal for the calculator. In the end the calculators are using formulas derived from empirical data.

OTOH Sonnet will give the right answer based on the actual geometry you provide. In Sonnet you define a PCB stackup, the surroundings and PCB layers. From there you can run a simulation. The free version has limits where it comes to memory use (which in turn limits size versus granularity).

[ogden]

Video about trace impedances: https://youtu.be/U60y4JC0Wxs?t=1

[cgroen]

Thanks for all the input and discussions so far, was very helpful and informative!

I have just ordered the board below, I'll get back once it arrives and I have it assembled. I selected to get it with HASL surface instead of ENIG as JLCPCB does not do ENIG boards before feb 8 again (CNY)
(I have ordered 5 pcs, if any of you wants one of the 4 "leftovers" you can have it for free, except for the shipping from me to you Only caveat is that you publish whatever you find out here in this thread  )

[Gerhard_dk4xp]

Everybody seems to do just this. We just had a discussion about solder mask effects
on usenet sci.electronics.design which is mirrored by google groups.
JL found out that the solder mask has no visible effect on the TDR (other manufacturer).
JohnL also said that the SMAs with the thick inner conductor have 100 Ohms in air
already without any board attached. I believe that.

I also tested the JLCPCB process with an Agilent 54754A TDR.
The 11.5 mil trace  seems to be absolutely correct. I drew it as 12 mil
in Altium, that makes it maybe a tad lower impedance when the
50 Ohm line in the 54754A is taken as a reference.

My SMA launchers were a disaster. I took the ones for a 2 layer board
and the center conductor was much too large.
The next board is on its way, with GND cut outs in the SMAs. I have no
idea where. Shipment tracking says it was in in Leipzig, Germany and
somehow it has jumped back to Hong Kong???
The board is a 15 GHz LMX2594 synthesizer to be shown in DUBUS 1/22
so I can't be too verbose bc I have promised the ius primae noctis to
Dubus , but methinks they'll tolerate a picture for a discussion.

Cheers, Gerhard

[rfclown]

Notice that Gerhard_dk4xp's board does not have ground on the top layer near the trace. This is microstrip. With ground on either side you have a grounded coplaner waveguide which has more capacitance per unit length than microstrip and therefore lower impedance (Zo=SQRT(L/C)) given the same dimensions (width, height). Solder mask has minimal effect. Conductor thickness has more effect than mask, which is why you need to calculate with the finished thickness (after plating). When doing boards with a thin dielectic on the top layer which makes for a thin 50 ohm line, if the pad for the SMA edge launch pin needs to be wider, you can eliminate ground directly under the pin pad to increase the dielectric thickness. I'll calculate what the pin pad width will be (to get 50 ohms) if the ground is on layer 3, or 4, or 5... I'll chose a ground reference layer for the pin pad that gives me an appropriate width for soldering the SMA pin.